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| 型号： | ADA4856-3YCP-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADA4856-3YCP |
| 标准包装： | 1 |
| 系列： | * |
ADA4856-3
Data Sheet
Rev. B | Page 16 of 20
SINGLE-SUPPLY OPERATION
The ADA4856-3 can operate in single-supply applications.
Figure 47 shows the schematic for a single 5 V supply video
driver. Resistors R2 and R4 establish the midsupply reference.
Capacitor C2 is the bypass capacitor for the midsupply reference.
Capacitor C1 is the input coupling capacitor, and C6 is the output
coupling capacitor. Capacitor C5 prevents constant current from
being drawn through the internal gain set resistor. Resistor R3
sets the ac input impedance of the circuit.
For more information on single-supply operation of op amps,
see “Avoiding Op-Amp Instability Problems In Single-Supply
Applications”, Analog Dialogue, Volume 35, Number 2, March-
May, 2001, at www.analog.com.
C2
1F
R2
50k
R4
50k
R3
1k
C1
22F
R1
50
C6
220F
R5
75
R6
75
C5
22F
ADA4856-3
+5V
07
68
6-
03
5
VOUT
VIN
–VS
C3
2.2F
C4
0.01F
+5V
Figure 47. AC-Coupled, Single-Supply Video Driver Schematic
In addition, the ADA4856-3 can be configured in dc-coupled,
single-supply operation. The common-mode input voltage
can go about 200 mV below ground, which makes it a true single-
supply part. However, in video applications, the black level is set
at 0 V, which means that the output of the amplifier must go to
the ground level as well. This part has a rail-to-rail output stage;
it can go as close as 100 mV from either rail. Figure 48 shows
the schematic for adding 50 mV dc offset to the input signal so
that the output is not clipped while still properly terminating
the input with 75 Ω.
07
68
6-
15
6
R1
3.74k
U1
R2
76.8
R3
75
R4
75
ADA4856-3
5V
VOUT
VIN
–VS
C1
10F
C2
0.1F
5V
Figure 48. DC-Coupled Single Supply Video Driver Schematic
POWER DOWN
The ADA4856-3 is equipped with a PD (power-down) pin for
all three amplifiers. This allows the user to reduce the quiescent
supply current when an amplifier is inactive. The power-down
threshold levels are derived from the voltage applied to the +VS
pin. When used in single-supply applications, this is especially
useful with conventional logic levels. The amplifier is enabled
when the voltage applied to the PD pin is greater than +VS 1.25 V.
In a 5 V single-supply application, the typical threshold voltage
is +3.75 V, and in a 3.3 V dual-supply application, the typical
threshold voltage is +2 V. The amplifier is also enabled when the
PD pin is left floating (not connected). However, the amplifier is
powered down when the voltage on the PD pin is lower than 2.5 V
from +VS. If the PD pin is not used, it is best to connect it to the
positive supply
Table 6. Power-Down Voltage Control
PD Pin
5 V
±2.5 V
3.3 V
Not Active
>3.75 V
>1.25 V
>2.05 V
Active
<2 V
<0 V
<1.3 V
LAYOUT CONSIDERATIONS
As is the case with all high speed applications, careful attention
to printed circuit board (PCB) layout details prevents associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the
board to provide a low impedance return path. Removing the
ground plane on all layers from the area near the input and output
pins reduces stray capacitance. Locate termination resistors and
loads as close as possible to their respective inputs and outputs.
Keep input and output traces as far apart as possible to minimize
coupling (crosstalk) though the board. Adherence to microstrip
or stripline design techniques for long signal traces (greater than
about 1 inch) is recommended.
POWER SUPPLY BYPASSING
Careful attention must be paid to bypassing the power supply pins
of the ADA4856-3. Use high quality capacitors with low equivalent
series resistance (ESR), such as multilayer ceramic capacitors
(MLCCs), to minimize supply voltage ripple and power dissipation.
A large, usually tantalum, 10 μF to 47 μF capacitor located in
proximity to the ADA4856-3 is required to provide good
decoupling for lower frequency signals. In addition, locate 0.1 μF
MLCC decoupling capacitors as close to each of the power supply
pins as is physically possible, no more than 1/8 inch away. The
ground returns should terminate immediately into the ground
plane. Locating the bypass capacitor return close to the load
return minimizes ground loops and improves performance.
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