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参数资料
| 型号： | ADA4857-2YCP-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADA4857-2YCP |
| 标准包装： | 1 |
| 每 IC 通道数： | 2 - 双 |
| 放大器类型： | 电压反馈 |
| 板类型： | 裸（未填充） |
| 已供物品： | 板 |
| 已用 IC / 零件： | 16-LFCSP 封装 |
ADA4857-1/ADA4857-2
Data Sheet
Rev. C | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
11 V
Power Dissipation
Common-Mode Input Voltage
VS + 0.7 V to +VS 0.7 V
Differential Input Voltage
±VS
Exposed Paddle Voltage
VS
Storage Temperature Range
65°C to +125°C
Operating Temperature Range
40°C to +125°C
Lead Temperature (Soldering, 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4.
Package Type
θJA
θJC
Unit
8-Lead SOIC
115
15
°C/W
8-Lead LFCSP
94.5
34.8
°C/W
16-Lead LFCSP
68.2
19
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4857 is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the properties of the plastic change. Even temporarily
exceeding this temperature limit may change the stresses that
the package exerts on the die, permanently shifting the parametric
performance of the ADA4857. Exceeding a junction temperature of
175°C for an extended period can result in changes in silicon
devices, potentially causing degradation or loss of functionality.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
die due to the ADA4857 drive at the output. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS).
PD = Quiescent Power + (Total Drive Power Load Power)
(
)
L
OUT
L
OUT
S
D
R
V
R
V
I
V
P
2
–
2
×
+
×
=
RMS output voltages should be considered. If RL is referenced
to VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
(
) (
)
L
S
D
R
V
I
V
P
2
4
/
+
×
=
In single-supply operation with RL referenced to VS, the worst
case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads and exposed paddle from metal traces, through holes,
ground, and power planes reduces θJA.
Figure 4 shows the maximum power dissipation in the package
vs. the ambient temperature for the SOIC and LFCSP packages
on a JEDEC standard 4-layer board. θJA values are approximations.
0
0.5
1.0
1.5
2.0
2.5
3.0
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90 100 110 120
07040-
004
AMBIENT TEMPERATURE (°C)
MA
XI
MU
M
PO
W
ER
D
ISSI
PA
T
IO
N
(W
)
ADA4857-1 (SOIC)
ADA4857-1 (LFCSP)
ADA4857-2 (LFCSP)
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
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