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参数资料
| 型号： | ADA4857-2YCP-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADA4857-2YCP |
| 标准包装： | 1 |
| 每 IC 通道数： | 2 - 双 |
| 放大器类型： | 电压反馈 |
| 板类型： | 裸（未填充） |
| 已供物品： | 板 |
| 已用 IC / 零件： | 16-LFCSP 封装 |
ADA4857-1/ADA4857-2
Data Sheet
Rev. C | Page 16 of 20
APPLICATIONS INFORMATION
POWER-DOWN OPERATION
The PD pin is used to power down the chip, which reduces the
quiescent current and the overall power consumption. It is low
enabled, which means that the chip is on with full power when
the PD pin input voltage is low (see Table 8). Note that PD does not
put the output in a high-Z state, which means that the ADA4857
should not be used as a multiplexer.
Table 8. PD Operation Table Guide
Supply Voltage
Condition
±5 V
±2.5 V
+5 V
Enabled
≤+0.8 V
≤1.7 V
≤+0.8 V
Powered down
≥+3 V
≥+0.5 V
≥+3 V
CAPACITIVE LOAD CONSIDERATIONS
When driving a capacitive load using the SOIC package, RSNUB is
used to reduce the peaking (see Figure 47). An optimum resistor
value of 40 is found to maintain the peaking within 1 dB for
any capacitive load up to 40 pF.
RECOMMENDED VALUES FOR VARIOUS GAINS
Table 9 provides a useful reference for determining various gains
and associated performance. RF and RG are kept low to minimize
their contribution to the overall noise performance of the amplifier.
Table 9. Various Gain and Recommended Resistor Values Associated with Conditions; VS = ±5 V, TA = 25°C, RL = 1 k, RT = 49.9
Gain
RS () (CSP/SOIC)
RF ()
RG ()
3 dB SS BW (MHz)
(CSP/SOIC)
Slew Rate (V/s),
VOUT = 2 V Step
ADA4857 Voltage
Noise (nV/√Hz), RTO
Total System
Noise (nV/√Hz), RTO
+1
0/100
0
N/A
850/750
2350
4.4
4.49
+2
0/0
499
360/320
1680
8.8
9.89
+5
0/0
499
124
90/89
516
22.11
23.49
+10
0/0
499
56.2
43/40
213
43.47
45.31
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