
ADATE302-02
Rev. A | Page 45 of 58
DETAILS OF REGISTERS
Table 22. PE/PMU Enable (ADDR[4:0] = 0x0C)
Bit
Name
Description
Data[2]
PMU enable
0 = disable PMU force output and clamps, place PMU in MV mode
1 = enable PMU force output
When set to 0, the PMU State bits are ignored, except for PMU Sense Path (Data[7]).
Data[1]
Force VT
0 = normal driver operation
1 = force driver to VT
See
Table 30 for complete functionality of this bit.
Data[0]
PE disable
0 = enable driver functions
1 = disable driver (low leakage)
See
Table 30 for complete functionality of this bit.
Table 23. Channel State (ADDR[4:0] = 0x0D)
Bit
Name
Description
Data[2]
HVOUT mode select
0 = HVOUT driver in low impedance
1 = enable HVOUT driver
This bit affects Channel 0 only. Ensure that Channel 0 bit in SPI write is active.
Channel 1 bit in SPI write is don’t care.
Data[1]
Load enable
0 = disable load
1 = enable load
See
Table 30 for complete functionality of this bit.
Data[0]
Driver high-Z/VT
0 = enable driver high-Z function
1 = enable driver VTERM function
See
Table 30 for complete functionality of this bit.
Table 24. PMU State (ADDR[4:0] = 0x0E)1, 2 Bit
Name
Description
Data[9:8]
PMU input selection
00 = VDUTGND (calibrated for 0.0 V voltage reference)
01 = 2.5 V + VDUTGND (calibrated for 0.0 A current reference)
1X = PMUDAC
Data[7]
PMU sense path
0 = internal sense
1 = external sense
Data[6]
Reserved
Data[5]
PMU clamp enable
0 = disable clamps
1 = enable clamps
Data[4]
PMU measure V/I
0 = measure voltage mode
1 = measure current mode
Data[3]
PMU force V/I
0 = force voltage mode
1 = force current mode
Data[2:0]
PMU range
0XX = Range E (2 μA)
100 = Range D (20 μA)
101 = Range C (200 μA)
110 = Range B (2 mA)
111 = Range A (25 mA)
1 Note that when the ADDR[4:0] = 0x0C PMU enable bit (Data[2]) = 0, the PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage
mode. Data[9:8] and Data[6:0] of the PMU state register are ignored, and only Data[7], the PMU sense path bit, is valid.
2 X = don’t care.