参数资料
| 型号： | ADATE304BBCZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 33/52页 |
| 文件大小： | 0K |
| 描述： | IC DCL ATE 200MHZ DUAL 84CSPBGA |
| 标准包装： | 1 |
| 类型： | DCL |
| 应用： | 自动测试设备 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 84-TFBGA，CSPBGA |
| 供应商设备封装： | 84-CSPBGA（9x9） |
| 包装： | 托盘 |
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ADATE304
Rev. 0 | Page 39 of 52
DETAILS OF REGISTERS
Table 21. PE/PMU Enable (ADDR[4:0] = 0x0C)
Bit
Name
Description
DATA[2]
PMU enable
0 = disable PMU force output and clamps, place PMU in MV mode
1 = enable PMU force output
When set to 0, the PMU state bits are ignored, except for the PMU sense path (DATA[7])
DATA[1]
Force VT
0 = normal driver operation
1 = force driver to VT
See Table 29 for complete functionality of this bit
DATA[0]
PE disable
0 = enable driver functions
1 = disable driver (low leakage)
See Table 29 for complete functionality of this bit
Table 22. Channel State (ADDR[4:0] = 0x0D)
Bit
Name
Description
DATA[2]
HV mode select
0 = HV driver in low impedance.
1 = enable HV driver.
This bit affects Channel 0 only. Ensure that the Channel 0 bit in SPI write is active.
Channel 1 bit in SPI write is don’t care.
DATA[1]
Load enable
0 = disable load.
1 = enable load.
See Table 29 for complete functionality of this bit.
DATA[0]
Driver high-Z or VT
0 = enable Driver high-Z function.
1 = enable Driver VTERM function.
See Table 29 for complete functionality of this bit.
Table 23. PMU State (ADDR[4:0] = 0x0E)1, 2
Bit
Name
Description
DATA[9:8]
PMU input selection
00 = VDUTGND (calibrated for 0.0 V voltage reference)
01 = 2.5 V + VDUTGND (calibrated for 0.0 A current reference)
1X = PMUDAC
DATA[7]
PMU sense path
0 = internal sense
1 = external sense
DATA[6]
Reserved
DATA[5]
PMU clamp enable
0 = disable clamps
1 = enable clamps
DATA[4]
PMU measure voltage or current
0 = measure voltage mode
1 = measure current mode
DATA[3]
PMU force voltage or current
0 = force voltage mode
1 = force current mode
DATA[2:0]
PMU range
0XX = 2 μA range
100 = 20 μA range
101 = 200 μA range
110 = 2 mA range
111 = 32 mA range
1 Note that when ADDR[4:0] = 0x0C, the PMU enable bit (DATA[2]) = 0, PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage mode.
PMU State DATA[9:8] and DATA[6:0] are ignored, and only the DATA[7] PMU sense path is valid.
2 X means don’t care.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADATE305 | 制造商:AD 制造商全称:Analog Devices 功能描述:250 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH |
| ADATE305BSVZ | 功能描述:IC DCL ATE 250MHZ DUAL 100TQFP RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| ADATE306BBCZ | 制造商:Analog Devices 功能描述: |
| ADATE318 | 制造商:AD 制造商全称:Analog Devices 功能描述:600 MHz Dual Integrated DCL with PPMU, VHH Drive Capability, Level Setting DACs, and On-Chip |
| ADATE318BCPZ | 制造商:Analog Devices 功能描述:600 MHZ DUAL INTEGRATED DCL WITH PPMU, VHH DRIVE CAPABILITY, - Trays |
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