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参数资料
| 型号： | ADAU1446YSTZ-3A-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/92页 |
| 文件大小： | 0K |
| 描述： | IC SIGMADSP 175MHZ 100LQFP |
| 标准包装： | 1,000 |
| 系列： | SigmaDSP® |
| 类型： | 音频处理器 |
| 应用： | 车载音频 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（16x16） |
| 包装： | 带卷 (TR) |
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ADAU1445/ADAU1446
Rev. A | Page 12 of 92
Pin No.
Mnemonic
Type1
Description
34
MP6
D_IO
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
35
MP5
D_IO
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
36
MP4
D_IO
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
40
VDRIVE
A_OUT
Regulator Drive. Supplies the drive current for the 1.8 V regulator. The base of the voltage regulator’s
external PNP transistor is driven from VDRIVE.
41
XTALO
A_OUT
Crystal Oscillator Output. A 100 Ω damping resistor should be connected between this pin and the
crystal. This output should not be used to directly drive a clock to another IC; the CLKOUT pin
exists for this purpose. If the crystal oscillator is not used, the XTALO pin can be left unconnected.
42
XTALI
A_IN
Crystal Oscillator Input. This pin provides the master clock for the ADAU1445/ADAU1446. If the
ADAU1445/ADAU1446 generate the master clock in the system, this pin should be connected to
the crystal oscillator circuit. If the ADAU1445/ADAU1446 are slaves to an external master clock, this
pin should be connected to the master clock signal generated by another IC.
43
PLL_FILT
A_OUT
Phase-Locked Loop Filter. Two capacitors and a resistor must be connected to this pin as shown in
44
PVDD
PWR
Phase-Locked Loop Supply. Provides the 3.3 V power supply for the PLL. This should be decoupled
to PGND with a100 nF capacitor.
45
PGND
PWR
Phase-Locked Loop Ground. Ground for the PLL supply. The AGND, DGND, and PGND pins can be
tied directly together in a common ground plane. PGND should be decoupled to PVDD with a
100 nF capacitor.
46
SPDIFI
D_IN
S/PDIF Input. Accepts digital audio data in the S/PDIF format. When not used, this pin can be left
disconnected.
47
SPDIFO
D_OUT
S/PDIF Output. Outputs digital audio data in the S/PDIF format. When not used, this pin can be left
disconnected.
48
AVDD
PWR
Analog Supply. 3.3 V analog supply for the auxiliary ADC. This pin should be decoupled to AGND
with a 100 nF capacitor.
49
AGND
PWR
Analog Ground. Ground for the analog supply. This pin should be decoupled to AVDD with a
100 nF capacitor.
53
CLKOUT
D_OUT
Master Clock Output. Used to output a master clock to other ICs in the system. Set using the
CLKMODEx pins. When not used, this pin can be left disconnected.
54
RESET
D_IN
Reset. Active-low reset input. Reset is triggered on a high-to-low edge and exited on a low-to-high
edge. For detailed information about initialization, see the Power-Up Sequence section. A reset
event sets all RAMs and registers to their default values.
55
MP3/ADC3
D_IO,
A_IN
Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 3. When not used, this pin can
be left disconnected.
56
MP2/ADC2
D_IO,
A_IN
Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 2. When not used, this pin can
be left disconnected.
57
MP1/ADC1
D_IO,
A_IN
Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 1. When not used, this pin can
be left disconnected.
58
MP0/ADC0
D_IO,
A_IN
Multipurpose, General-Purpose IO/Auxiliary ADC Input 0. When not used, this pin can be left
disconnected.
59
PLL1
D_IN
Phase-Locked Loop Mode Select Pin 1.
60
PLL0
D_IN
Phase-Locked Loop Mode Select Pin 0.
61
SDATA_OUT8
D_OUT
Serial Data Port 0 Output. When not used, this pin can be left disconnected.
64
BCLK11
D_IO
Bit Clock, Output Clock Domain 2. This pin is bidirectional, with the direction depending on whether the
Output Clock Domain 2 is set up as a master or slave. When not used, this pin can be left disconnected.
65
LRCLK11
D_IO
Frame Clock, Output Clock Domain 2. This pin is bidirectional, with the direction depending on
whether the Output Clock Domain 2 is set up as a master or slave. When not used, this pin can be
left disconnected.
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相关代理商/技术参数 |
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| ADAU1450WBCPZ | 功能描述:IC AUDIO PROCESSOR 72LFCSP 制造商:analog devices inc. 系列:SigmaDSP? 包装:托盘 零件状态:有效 类型:Sigma 接口:I2C，SPI 时钟速率:147.456MHz 非易失性存储器:- 片载 RAM:64KB 电压 - I/O:3.3V 电压 - 内核:1.20V 工作温度:-40°C ~ 105°C（TA） 安装类型:表面贴装 封装/外壳:72-VFQFN 裸露焊盘，CSP 供应商器件封装:72-LFCSP-VQ（10x10） 标准包装:1 |
| ADAU1450WBCPZ-RL | 功能描述:IC AUDIO PROCESSOR 72LFCSP 制造商:analog devices inc. 系列:SigmaDSP? 包装:剪切带（CT） 零件状态:在售 类型:Sigma 接口:I2C，SPI 时钟速率:147.456MHz 非易失性存储器:- 片载 RAM:64KB 电压 - I/O:3.30V 电压 - 内核:1.20V 工作温度:-40°C ~ 105°C（TA） 安装类型:表面贴装 封装/外壳:72-VFQFN 裸露焊盘，CSP 供应商器件封装:72-LFCSP-VQ（10x10） 标准包装:1 |
| ADAU1451WBCPZ | 功能描述:IC AUDIO PROCESSOR 72LFCSP 制造商:analog devices inc. 系列:SigmaDSP? 包装:托盘 零件状态:有效 类型:Sigma 接口:I2C，SPI 时钟速率:294.912MHz 非易失性存储器:- 片载 RAM:96kB 电压 - I/O:3.3V 电压 - 内核:1.20V 工作温度:-40°C ~ 105°C（TA） 安装类型:表面贴装 封装/外壳:72-VFQFN 裸露焊盘，CSP 供应商器件封装:72-LFCSP-VQ（10x10） 标准包装:1 |
| ADAU1451WBCPZ-RL | 功能描述:IC AUDIO PROCESSOR 72LFCSP 制造商:analog devices inc. 系列:SigmaDSP? 包装:剪切带（CT） 零件状态:在售 类型:Sigma 接口:I2C，SPI 时钟速率:294.912MHz 非易失性存储器:- 片载 RAM:96kB 电压 - I/O:3.30V 电压 - 内核:1.20V 工作温度:-40°C ~ 105°C（TA） 安装类型:表面贴装 封装/外壳:72-VFQFN 裸露焊盘，CSP 供应商器件封装:72-LFCSP-VQ（10x10） 标准包装:1 |
| ADAU1452WBCPZ | 功能描述:IC AUDIO PROCESSOR 72LFCSP 制造商:analog devices inc. 系列:SigmaDSP? 包装:托盘 零件状态:有效 类型:Sigma 接口:I2C，SPI 时钟速率:294.912MHz 非易失性存储器:- 片载 RAM:192kB 电压 - I/O:3.3V 电压 - 内核:1.20V 工作温度:-40°C ~ 105°C（TA） 安装类型:表面贴装 封装/外壳:72-VFQFN 裸露焊盘，CSP 供应商器件封装:72-LFCSP-VQ（10x10） 标准包装:1 |
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