参数资料
型号: ADAU1702JSTZ
厂商: Analog Devices Inc
文件页数: 15/52页
文件大小: 0K
描述: IC AUDIO PROC 2ADC/4DAC 48-LQFP
标准包装: 1
系列: SigmaDSP®
类型: 音频处理器
应用: 车载,监视器,MP3
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 托盘
产品目录页面: 776 (CN2011-ZH PDF)
ADAU1702
Rev. C | Page 22 of 52
CONTROL PORTS
The ADAU1702 can operate in one of three control modes:
I2C control
SPI control
Self-boot (no external controller)
The ADAU1702 has both a 4-wire SPI control port and a
2-wire I2C bus control port. Each can be used to set the RAMs
and registers. When the SELFBOOT pin is low at power-up, the
part defaults to I2C mode but can be put into SPI control mode
by pulling the CLATCH/WP pin low three times. When the
SELFBOOT pin is set high at power-up, the ADAU1702 loads
its program, parameters, and register settings from an external
EEPROM on startup.
The control port is capable of full read/write operation for all
addressable memory and registers. Most signal processing
parameters are controlled by writing new values to the parameter
RAM using the control port. Other functions, such as mute and
input/output mode control, are programmed by writing to the
registers.
All addresses can be accessed in a single address mode or a
burst mode. The first byte (Byte 0) of a control port write
contains the 7-bit chip address plus the R/W bit. The next two
bytes (Byte 1 and Byte 2) together form the subaddress of the
memory or register location within the ADAU1702. This
subaddress must be two bytes because the memory locations
within the ADAU1702 are directly addressable and their sizes
exceed the range of single byte addressing. All subsequent bytes
(starting with Byte 3) contain the data, such as control port data,
program data, or parameter data. The number of bytes per word
depends on the type of data that is being written. The exact formats
for specific types of writes are shown in
.
The ADAU1702 has several mechanisms for updating signal
processing parameters in real time without causing pops or
clicks. If large blocks of data need to be downloaded, the output
of the DSP core can be halted (using the CR bit in the DSP core
control register (Address 2076)), new data can be loaded, and
then the device can be restarted. This is typically done during
the booting sequence at startup or when loading a new program
into RAM. In cases where only a few parameters need to be
changed, they can be loaded without halting the program. To
avoid unwanted side effects while loading parameters on the fly, the
SigmaDSP provides safeload registers. The safeload registers can
be used to buffer a full set of parameters (for example, the five
coefficients of a biquad) and then transfer these parameters into
the active program within one audio frame. The safeload mode
uses internal logic to prevent contention between the DSP core
and the control port.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 13 details these
multiple functions.
Table 13. Control Port Pins and SELFBOOT Pin Functions
Pin
I2C Mode
SPI Mode
Self-Boot
SCL/CCLK
SCL—input
CCLK—input
SCL—output
SDA/COUT
SDA—open-collector output
COUT—output
SDA—open-collector output
ADDR1/CDATA/WB
ADDR1—input
CDATA—input
WB—writeback trigger
CLATCH/WP
Unused input—tie to ground or IOVDD
CLATCH—input
WP—EEPROM write protect, open-collector output
ADDR0
ADDR0—input
Unused input—tie to ground or IOVDD
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