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| 型号： | ADAU1761BCPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/92页 |
| 文件大小： | 0K |
| 描述： | IC SIGMADSP CODEC PLL 32LFCSP |
| 设计资源： | Stereo Digital Microphone Input Using ADAU1761 and ADMP421 (CN0078) |
| 标准包装： | 5,000 |
| 系列： | SigmaDSP® |
| 类型： | 音频编解码器 |
| 数据接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 数量： | 2 / 2 |
| 三角积分调变： | 是 |
| 电压 - 电源，模拟： | 1.8 V ~ 3.65 V |
| 电压 - 电源，数字： | 1.63V ~ 3.65V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-ADAU1761Z-ND - BOARD EVAL FOR ADAU1761 |
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ADAU1761
Rev. C | Page 32 of 92
AUTOMATIC LEVEL CONTROL (ALC)
The ADAU1761 contains a hardware automatic level control
(ALC). The ALC is designed to continuously adjust the PGA
gain to keep the recording volume constant as the input level
varies.
For optimal noise performance, the ALC uses the analog PGA
to adjust the gain instead of using a digital method. This ensures
that the ADC noise is not amplified at low signal levels.
Extremely small gain step sizes are used to ensure high audio
quality during gain changes.
To use the ALC function, the inputs must be applied either
differentially or pseudo-differentially to input pins LINN and
LINP, for the left channel, and RINN and RINP, for the right
channel. The ALC function is not available for the auxiliary line
input pins, LAUX and RAUX.
A block diagram of the ALC block is shown in Figure 37. The
ALC logic receives the ADC output signals and analyzes these
digital signals to set the PGA gain. The ALC control registers
are used to control the time constants and output levels, as
described in this section.
07
68
0-
0
24
RIGHT
ADC
LEFT
ADC
MUTE
SERIAL
PORTS
ALC
DIGITAL
ANALOG
INPUT
LEFT
I2C
CONTROL
ANALOG
INPUT
RIGHT
PGA
–12dB TO +35.25dB
0.75dB STEP SIZE
Figure 37. ALC Architecture
ALC PARAMETERS
The ALC function is controlled with the ALC control registers
(Address 0x4011 through Address 0x4014) using the following
parameters:
ALCSEL[2:0]: The ALC select bits are used to enable the
ALC and set the mode to left only, right only, stereo, or
DSP. In stereo mode, the greater of the left or right inputs
is used to calculate the gain, and the same gain is then
applied to both the left and right channels. In DSP mode,
the PGA gain is controlled by the SigmaDSP core.
ALCTARG[3:0]: The ALC target is the desired input
recording level that the ALC attempts to achieve.
ALCATCK[3:0]: The ALC attack time sets how fast the
ALC starts attenuating after a sudden increase in input
level above the ALC target. Although it may seem that
the attack time should be set as fast as possible to avoid
clipping on transients, using a moderate value results in
better overall sound quality. If the value is too fast, the
ALC overreacts to very short transients, causing audible
gain-pumping effects, which sounds worse than using a
moderate value that allows brief periods of clipping on
transients. A typical setting for music recording is 384 ms.
A typical setting for voice recording is 24 ms.
ALCHOLD[3:0]: These bits set the ALC hold time. When
the output signal falls below the target output level, the
gain is not increased unless the output remains below the
target level for the period of time set by the hold time bits.
The hold time is used to prevent the gain from modulating
on a steady low frequency sine wave signal, which would
cause distortion.
ALCDEC[3:0]: The ALC decay time sets how fast the ALC
increases the PGA gain after a sudden decrease in input level
below the ALC target. A very slow setting can be used if the
main function of the ALC is to set a music recording level.
A faster setting can be used if the function of the ALC is to
compress the dynamic range of a voice recording. Using a
very fast decay time can cause audible artifacts such as noise
pumping or distortion. A typical setting for music recording
is 24.58 sec. A typical setting for voice recording is 1.54 sec.
ALCMAX[2:0]: The maximum ALC gain bits are used to
limit the maximum gain that can be programmed into the
ALC. This can be used to prevent excessive noise in the
recording for small input signals. Note that setting this
register to a low value may prevent the ALC from reaching
its target output level, but this behavior is often desirable to
achieve the best overall sound.
Figure 38 shows the dynamic behavior of the PGA gain for a
tone-burst input. The target output is achieved for three differ-
ent input levels, with the effect of attack, hold, and decay shown
in the figure. Note that for very small signals, the maximum PGA
gain may prevent the ALC from achieving its target level; in the
same way, for very large inputs, the minimum PGA gain may
prevent the ALC from achieving its target level (assuming that
the target output level is set to a very low value). The effects of
the PGA gain limit are shown in the input/output graph of
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相关代理商/技术参数 |
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| ADAU1772BCPZ | 功能描述:接口—CODEC Low Latency Noise and Power CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| ADAU1772BCPZ-R7 | 功能描述:接口—CODEC Low Latency Noise and Power CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| ADAU1772BCPZ-RL | 功能描述:接口—CODEC Low Latency Noise and Power CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| ADAU1777BCBZRL | 功能描述:LOW LATENCY NOISE AND POWER CODE 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:在售 类型:音频 数据接口:I2C，SPI? 分辨率（位）:24 b ADC/DAC 数:4 / 2 三角积分:无 信噪比，ADC/DAC（db）（典型值）:102 / 108 动态范围，ADC/DAC（db）（典型值）:- 电压 - 电源，模拟:1.71 V ~ 3.63 V 电压 - 电源，数字:1.045 V ~ 1.98 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:36-WFBGA，WLCSP 供应商器件封装:36-WLCSP（3.77x3.20） 标准包装:5,000 |
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