- 您现在的位置：买卖IC网 > PDF目录378276 > ADC0800 (National Semiconductor Corporation) ECONOLINE: REC3-S_DRW(Z)/H* - 3W DIP Package- 1kVDC Isolation- Wide Input 2:1 & 4:1- Regulated Output- 100% Burned In- UL94V-0 Package Material- Continuous Short Circiut Protection- Efficiency to 80% PDF资料下载
参数资料
| 型号： | ADC0800 |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | ECONOLINE: REC3-S_DRW(Z)/H* - 3W DIP Package- 1kVDC Isolation- Wide Input 2:1 & 4:1- Regulated Output- 100% Burned In- UL94V-0 Package Material- Continuous Short Circiut Protection- Efficiency to 80% |
| 中文描述： | ADC0800 8位A / D转换器 |
| 文件页数： | 3/10页 |
| 文件大小： | 166K |
| 代理商： | ADC0800 |
Timing Diagram
TL/H/5670–2
Data is complementary binary (full scale is all ‘‘0’s’’ output).
Application Hints
OPERATION
The ADC0800 contains a network with 256-300
X
resistors
in series. Analog switch taps are made at the junction of
each resistor and at each end of the network. In operation,
a reference (10.00V) is applied across this network of 256
resistors. An analog input (V
IN
) is first compared to the cen-
ter point of the ladder via the appropriate switch. If V
IN
is
larger than V
REF
/2, the internal logic changes the switch
points and now compares V
IN
and
*/4
V
REF
. This process,
known as successive approximation, continues until the
best match of V
IN
and V
REF
/N is made. N now defines a
specific tap on the resistor network. When the conversion is
complete, the logic loads a binary word corresponding to
this tap into the output latch and an end of conversion
(EOC) logic level appears. The output latches hold this data
valid until a new conversion is completed and new data is
loaded into the latches. The data transfer occurs in about
200 ns so that valid data is present virtually all the time in
the latches. The data outputs are activated when the Output
Enable is high, and in TRI-STATE when Output Enable is
low. The Enable Delay time is approximately 200 ns. Each
conversion requires 40 clock periods. The device may be
operated in the free running mode by connecting the Start
Conversion line to the End of Conversion line. However, to
ensure start-up under all possible conditions, an external
Start Conversion pulse is required during power up condi-
tions.
REFERENCE
The reference applied across the 256 resistor network de-
termines the analog input range. V
REF
e
10.00V with the top
of the R-network connected to 5V and the bottom connect-
ed to
b
5V gives a
g
5V range. The reference can be level
shifted between V
SS
and V
GG
. However, the voltage, ap-
plied to the top of the R-network (pin 15), must not exceed
V
SS
, to prevent forward biasing the on-chip parasitic silicon
diodes that exist between the P-diffused resistors (pin 15)
and the N-type body (pin 10, V
SS
). Use of a standard logic
power supply for V
SS
can cause problems, both due to initial
voltage tolerance and changes over temperature. A solution
is to power the V
SS
line (15 mA max drain) from the output
of the op amp that is used to bias the top of the
R-network (pin 15). The analog input voltage and the volt-
age that is applied to the bottom of the R-network (pin 5)
must be at least 7V above the
b
V
GG
supply voltage to
ensure adequate voltage drive to the analog switches.
Other reference voltages may be used (such as 10.24V). If a
5V reference is used, the analog range will be 5V and accu-
racy will be reduced by a factor of 2. Thus, for maximum
accuracy, it is desirable to operate with at least a 10V refer-
ence. For TTL logic levels, this requires 5V and
b
5V for the
R-network. CMOS can operate at the 10 V
DC
V
SS
level and
a single 10 V
DC
reference can be used. All digital voltage
levels for both inputs and outputs will be from ground to
V
SS
.
ANALOG INPUT AND SOURCE RESISTANCE
CONSIDERATIONS
The lead to the analog input (pin 12) should be kept as short
as possible. Both noise and digital clock coupling to this
input can cause conversion errors. To minimize any input
errors, the following source resistance considerations
should be noted:
For R
S
s
5k
No analog input bypass capacitor re-
quired, although a 0.1
m
F input bypass
capacitor will prevent pickup due to un-
avoidable series lead inductance.
For 5k
k
R
S
s
20k
A 0.1
m
F capacitor from the input (pin
12) to ground should be used.
For R
S
l
20k
Input buffering is necessary.
If the overall converter system requires lowpass filtering of
the analog input signal, use a 20 k
X
or less series resistor
for a passive RC section or add an op amp RC active low-
pass filter (with its inherent low output resistance) to ensure
accurate conversions.
CLOCK COUPLING
The clock lead should be kept away from the analog input
line to reduce coupling.
LOGIC INPUTS
The logical ‘‘1’’ input voltage swing for the Clock, Start Con-
version and Output Enable should be (V
SS
b
1.0V).
3
相关PDF资料 |
PDF描述 |
|---|---|
| ADC08031 | 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, <BR> Voltage Reference, and Track/Hold Function |
| ADC08031CIN | 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, <BR> Voltage Reference, and Track/Hold Function |
| ADC08031CIWM | 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, Voltage Reference, and Track/Hold Function |
| ADC08034 | 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, Voltage Reference, and Track/Hold Function(8位高速串行输入/输出A/D转换器带多路选择，电压基准和跟踪/保持功能) |
| ADC08038 | 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, Voltage Reference, and Track/Hold Function(8位高速串行输入/输出A/D转换器带多路选择，电压基准和跟踪/保持功能) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADC08004-1CD | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:CMOS 8-bit A/D converters |
| ADC08004-1CN | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:CMOS 8-bit A/D converters |
| ADC08004-1LCD | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:CMOS 8-bit A/D converters |
| ADC08004-1LCN | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:CMOS 8-bit A/D converters |
| ADC0800PCD | 制造商:NSC 制造商全称:National Semiconductor 功能描述:ADC0800 8-Bit A/D Converter |
发布紧急采购，3分钟左右您将得到回复。