参数资料
型号: ADC08061BIN
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: ADC
英文描述: TIMER DIGITAL LED RoHS Compliant: Yes
中文描述: 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, DIP20
封装: DIP-20
文件页数: 2/16页
文件大小: 307K
代理商: ADC08061BIN
Connection Diagrams
Ordering Information
Industrial (40C
T
A
85C)
ADC08061BIN, ADC08062BIN
ADC08061CIWM, ADC08062CIWM
Package
N20A
M20B
Pin Description
V
IN
,
V
IN1–8
GND–50 mV
V
V
+
+ 50 mV. The
ADC08061 has a single input (V
IN
) and the
ADC08062
has
(V
IN1–2
).
DB0–DB7 TRI-STATE data outputs— bit 0 (LSB) through
bit 7 (MSB).
WR /RDY
WR-RD Mode
(Logic high applied to MODE pin)
WR:
With CS low, the conversion is started on
the falling edge of WR. The digital result will be
strobed into the output latch at the end of con-
version (see Figures 2, 3, 4).
:
RD Mode
(Logic low applied to MODE pin)
RDY:
This is an open drain output (no internal
pull-up device). RDY will go low after the falling
edge of CS and return high at the end of conver-
sion.
MODE
Mode:
Mode
(
RD
input— This pin is pulled to a logic low through
an internal 50 μA current sink when left uncon-
nected.
RD Mode
is selected if the MODE pin is left un-
connected or externally forced low. A complete
conversion is accomplished by pulling RD low
until output data appears.
WR-RD Mode
is selected when a high is applied
to the MODE pin. A conversion starts with the
WR signal’s rising edge and then using RD to
access the data.
RD
WR-RD Mode
(logic high on the MODE pin)
This is the active low Read input. With a logic
low applied to the CS pin, the TRI-STATE data
outputs (DB0–DB7) will be activated when RD
goes low (Figures 2, 3, 4).
RD Mode
(logic low on the MODE pin)
These are analog inputs. The input range is
a
two-channel
multiplexer
or
WR-RD
)
selection
With CS low, a conversion starts on the falling
edge of RD. Output data appears on DB0–DB7
at the end of conversion(see Figures 1, 5).
This is an active low output that indicates that a
conversion is complete and the data is in the
output latch. INT is reset by the rising edge of
RD.
This is the power supply ground pin. The ground
pin should be connected to a “clean” ground ref-
erence point.
These are the reference voltage inputs. They
may be placed at any voltage between GND
50 mV and V
+
+ 50 mV, but V
must be
greater than V
REF
. Ideally, an input voltage
equal to V
and an input voltage greater than V
REF+
1.5
LSB produces an output code of 255.
For the ADC08062, an input voltage on any un-
selected input that exceeds V
+
by more than
100 mV or is below GND by more than 100 mV
will create errors in a selected channel that is
operating within proper operating conditions.
This is the active low Chip Select input. A logic
low signal applied to this input pin enables the
RD and WR inputs. Internally, the CS signal is
ORed with RD and WR signals.
Overflow Output. If the analog input is higher
than V
1
2
LSB, OFL will be low at the end
of conversion. It can be used when cascading
two ADC08061s to achieve higher resolution (9
bits). This output is always active and does not
go into TRI-STATE as DB0–DB7 do. When OFL
is set, all data outputs remain high when the
ADC08061’s output data is read.
No connection.
INT
GND
V
REF
,
V
REF+
CS
OFL
NC
DS011086-14
Dual-In-Line and Wide-Body
Small-Outline
Packages N20A or M20B
DS011086-15
Dual-In-Line and Wide-Body
Small-Outline
Packages N20A or M20B
www.national.com
2
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