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| 型号： | ADC08138 |
| 厂商： | National Semiconductor Corporation |
| 元件分类： | 串行ADC |
| 英文描述： | 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, Voltage Reference, and Track/Hold Function(8位高速串行输入/输出A/D转换器带多路选择，电压基准和跟踪/保持功能) |
| 中文描述： | 8位高速串行I /办公自动化/ D的多路复用器选项，电压参考，并跟踪转换器/保持功能（8位高速串行输入/输出的A / D转换器带多路选择，电压基准和跟踪/保持功能） |
| 文件页数： | 15/21页 |
| 文件大小： | 483K |
| 代理商： | ADC08138 |
Functional Description
(Continued)
small (see Typical Performance Characteristics) to allow
direct conversions of transducer outputs providing less than
a 5V output span. Particular care must be taken with regard
to noise pickup, circuit layout and system error voltage
sources when operating with a reduced span due to the
increased sensitivity of the converter (1 LSB equals
V
REF/
256).
THE ANALOG INPUTS
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling proces-
sor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accu-
racy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected “+” and “” inputs for a conversion (60 Hz is
most typical). The time interval between sampling the “+”
input and then the “” input is
1
2
of a clock period. The
change in the common-mode voltage during this short time
interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:
where f
CM
is the frequency of the common-mode signal,
V
PEAK
is its peak voltage value
and f
CLK
is the A/D clock frequency.
For a 60Hz common-mode signal to generate a
1
4
LSB error
(
≈
5 mV) with the converter running at 250kHz, its peak value
would have to be 6.63V which would be larger than allowed
as it exceeds the maximum analog input limits.
Source resistance limitation is important with regard to the
DC leakage currents of the input multiplexer. While operating
near or at maximum speed bypass capacitors should not be
used if the source resistance is greater than 1k
. The
worst-case leakage current of
±
1μA over temperature will
create a 1mV input error with a 1k
source resistance.An op
amp RC active low pass filter can provide both impedance
buffering and noise filtering should a high impedance signal
source be required.
OPTIONAL ADJUSTMENTS
Zero Error
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, V
, is not ground
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any V
() input at this V
value. This
utilizes the differential mode operation of the A/D.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V
IN
() input and applying a small magnitude
positive voltage to the V
IN
(+) input. Zero error is the differ-
ence between the actual DC input voltage which is neces-
sary to just cause an output digital code transition from 0000
0000 to 0000 0001 and the ideal
1
2
LSB value (
1
2
LSB =
9.8mV for V
REF
= 5.000V
DC
).
Full Scale
A full-scale adjustment can be made by applying a differen-
tial input voltage which is 1
1
2
LSB down from the desired
analog full-scale voltage range and then adjusting the mag-
nitude of the V
IN input for a digital output code which is
just changing from 1111 1110 to 1111 1111 (See figure en-
titled “SpanAdjust; 0V
≤
V
≤
3V”). This is possible only with
the ADC08134 and ADC08138. (The reference is internally
connected to V
REF
IN of the ADC08131).
DS010749-17
a) Ratiometric
DS010749-18
b) Absolute
FIGURE 2. Reference Examples
A
www.national.com
15
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