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参数资料
| 型号： | ADC0816 |
| 厂商： | National Semiconductor Corporation |
| 元件分类： | 串行ADC |
| 英文描述： | 8-BitμP Compatible A/D Converters with 16-Channel Multiplexer(带16通道多路器的8位μP兼容A/D转换器) |
| 中文描述： | 8BitμP兼容的A / D转换器的16通道多路复用器（带16通道多路器的8位微处理器兼容的A / D转换器） |
| 文件页数： | 4/13页 |
| 文件大小： | 245K |
| 代理商： | ADC0816 |
Electrical Characteristics
(Continued)
Digital Levels and DC Specifications:
ADC0816CCN, ADC0817CCN— 4.75V
≤
V
CC
≤
5.25V, 40C
≤
T
A
≤
+85C unless other-
wise noted.
Symbol
Parameter
Conditions
CONTROL INPUTS
V
IN(1)
Logical “1” Input Voltage
V
IN(0)
Logical “0” Input Voltage
I
IN(1)
Logical “1” Input Current
V
IN
=15V
(The Control Inputs)
I
IN(0)
Logical “0” Input Current
V
IN
=0
(The Control Inputs)
I
CC
Supply Current
f
CLK
=640 kHz
DATA OUTPUTS AND EOC (INTERRUPT)
V
OUT(1)
Logical “1” Output Voltage
I
O
=360 μA, T
A
=85C
I
O
=300 μA, T
A
=125C
V
OUT(0)
Logical “0” Output Voltage
I
O
=1.6 mA
V
OUT(0)
Logical “0” Output Voltage EOC
I
O
=1.2 mA
I
OUT
TRI-STATE Output Current
V
O
=V
CC
V
O
=0
Min
Typ
Max
Units
V
CC
1.5
V
V
μA
1.5
1.0
1.0
μA
0.3
3.0
mA
V
CC
0.4
V
0.45
0.45
3.0
V
V
μA
μA
3.0
Electrical Characteristics
Timing Specifications:
V
CC
=V
REF(+)
=5V, V
REF()
=GND, t
r
=t
f
=20 ns and T
A
=25C unless otherwise noted.
Symbol
Parameter
t
WS
Minimum Start Pulse Width
(Figure 5) (Note 7)
t
WALE
Minimum ALE Pulse Width
(Figure 5)
t
s
Minimum Address Set-Up Time
(Figure 5)
T
H
Minimum Address Hold Time
(Figure 5)
t
D
Analog MUX Delay Time
R
S
=O
(Figure 5)
from ALE
t
H1
, t
H0
OE Control to Q Logic State
C
L
=50 pF, R
L
=10k (Figure 8)
t
1H,
t
0H
OE Control to Hi-Z
C
L
=10 pF, R
L
=10k (Figure 8)
t
C
Conversion Time
f
c
=640 kHz, (Figure 5) (Note 8)
f
c
Clock Frequency
t
EOC
EOC Delay Time
(Figure 5)
Conditions
Min
Typ
100
100
25
25
1
Max
200
200
50
50
2.5
Units
ns
ns
ns
ns
μs
125
125
100
640
250
250
116
1280
8+2μs
ns
ns
μs
kHz
Clock
Periods
pF
pF
90
10
0
C
IN
C
OUT
Input Capacitance
TRI-STATE Output
Capacitance
At Control Inputs
At TRI-STATE Outputs (Note 8)
10
10
15
15
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2:
All voltages are measured with respect to GND, unless otherwise specified.
Note 3:
A zener diode exists, internally, from V
CC
to GND and has a typical breakdown voltage of 7 V
DC
.
Note 4:
Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater
than the V
supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog V
does not exceed the supply voltage by more
than 100 mV, the output code will be correct. To achieve an absolute 0 V
DC
to 5 V
DC
input voltage range will therefore require a minimum supply voltage of 4.900
V
DC
over temperature variations, initial tolerance and loading.
Note 5:
Total unadjusted error includes offset, full-scale, and linearity errors. See Figure 3 None of these A/Ds requires a zero or full-scale adjust. However, if an
all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages can be
adjusted to achieve this. See Figure 13
Note 6:
Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has little
temperature dependence (Figure 6). See paragraph 4.0.
Note 7:
If start pulse is asynchronous with converter clock or if f
c
>
640 kHz, the minimum start pulse width is 8 clock periods plus 2 μs. For synchronous operation
at f
c
≤
640 kHz take start high within 100 ns of clock going low.
Note 8:
The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 9:
Human body model, 100 pF discharged through a 1.5 k
resistor.
www.national.com
4
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