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参数资料
| 型号： | ADC0851BIV |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 8-Bit Analog Data Acquisition and Monitoring Systems |
| 中文描述： | 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20 |
| 封装： | PLASTIC, LCC-20 |
| 文件页数： | 19/36页 |
| 文件大小： | 581K |
| 代理商： | ADC0851BIV |
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2.0 Memory Access Modes
(Continued)
Note that the memory address is clocked in with the MSB
(bit A3) first whereas the limit data is clocked in with the LSB
(bit L0) first.
Figure 3 shows the timing diagram for writing one limit. After
CS is brought low, the input word (DI) is clocked in starting
at the first rising edge of CLK. Taking CS high after the MSB
(bit L7) of the limit data is loaded completes the write opera-
tion.
2.2 WRITE ALL LIMITS MODE
This mode is used to update all memory locations in the limit
RAM. An 8-bit limit word is written to each memory location.
Note that there are four limit words for the ADC0851 and
sixteen limit words for the ADC0858. To initiate the opera-
tion of the device in the ‘‘write all limits’’ mode, the mode
address has to be 1 1 0 1 (see Table I). The data format for
the input word is as shown below.
Data Input (DI) WordDADC0851 or ADC0858
TL/H/11021–32
When writing all limits, memory address is not required. The
limit data is sequentially written into the RAM starting at the
location for CH0–Lower Limit and ending at; CH1–Upper
Limit for the ADC0851 (see Table IIa), CH7–Upper Limit for
ADC0858 (see Table IIb). Note that L0 corresponds to the
LSB of the limit data.
Figure 4 shows the timing diagram. After CS is brought low,
the input word (DI) is clocked in starting at the first rising
edge of CLK. The first four bits of D1 configure the device in
the ‘‘write all limits’’ mode. Next, the limit data is serially
clocked in. To complete the operation, CS should be
brought high after the data is loaded.
2.3 READ ONE LIMIT MODE
When the mode address is 1 0 1 1, the device is configured
in the ‘‘read one limit’’ mode. One 8-bit limit word can be
read from the RAM memory location pointed to by the limit
address. The data format for the input word is as shown
below.
Data Input (DI)DADC0851 or ADC0858
TL/H/11021–33
TL/H/11021–34
FIGURE 3. Timing Diagram for Write One Limit
TL/H/11021–35
FIGURE 4. Timing Diagram for Write All Limits
19
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PDF描述 |
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| ADC0851CIN | 8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0851CIV | 8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0858CIN | 8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0858CIV | 8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0881 | 8-Bit 20 MSPS Flash A/D Converter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADC0851CIJ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| ADC0851CIN | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0851CIV | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0851CMJ/883 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| ADC0852 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Multiplexed Comparator with 8-Bit Reference Divider |
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