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| 型号： | ADC0858BIV |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 8-Bit Analog Data Acquisition and Monitoring Systems |
| 中文描述： | 8-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20 |
| 封装： | PLASTIC, LCC-20 |
| 文件页数： | 16/36页 |
| 文件大小： | 581K |
| 代理商： | ADC0858BIV |
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3.0 Programming Information
(Continued)
limits while the odd addresses correspond to the upper lim-
its. The ADC0851 and ADC0858 both use four bits (A3–A0)
to address the limit RAM but the ADC0851 only decodes
the two LSBs while ignoring the two MSBs. The ADC0858
decodes all four bits thus yielding sixteen limit addresses.
3.4 STATUS AND CHANNEL TAG DATA
(S3, S2, . . . , S0, ADC0851; S15, S14, . . . , S0, ADC0858)
(T3, T2, . . . , T0)
During watchdog mode, immediately after one analog input
is determined to be outside of its programmed window limit,
its channel number is stored in the channel tag register and
the remaining inputs are checked one more time and the
pass/fail status of each input is stored in the status register.
When the microprocessor receives the interrupt signal, it
can read the status and channel tag data by pulling CS low
and clocking out the data.
3.5 CHANNEL CONFIGURATION DATA
(C11, C10, . . . C0)
The channel configuration data assigns the configuration of
the multiplexer. The data is comprised of twelve bits with
each group of three bits addressing an analog input channel
pair. Each channel pair can be configured for single-ended
operation, differential operation, one single ended channel
and one disabled channel, or both channels disabled. The
channel configuration data is required when the device is in
the watchdog or Auto A/D conversion mode.
3.6 CHANNEL INFORMATION DATA
(I3, I2, . . . I0)
This data is used by the ADC0851/8 only when the device is
configured in the ‘‘One A/D conversion’’ mode. The chan-
nel information data assigns the configuration of the multi-
plexer.
3.7 MODE ADDRESS (M3, M2, . . . M0)
The input word (DI) configures the ADC0851/8 for various
modes of operation. The first four bits of the input word
constitute the mode address which specifies the mode of
operation.
3.8 POWER FAIL BIT (P)
The ADC0851/8 is automatically configured to the watch-
dog mode upon power-up and an interrupt is immediately
generated after CS is pulled high. Pulling CS low produces a
17-bit data stream. The seventeenth bit of the output word
DO in the watchdog mode is the power fail bit, P. If the
output data is read after power-up then P will be at logical
‘‘1’’. Changing the mode of operation resets P to logical
‘‘0’’. Any subsequent power failure will cause the device to
configure in the watchdog mode upon power-up with P at
logical ‘‘1’’.
4.0 Initialization after Power-Up
The ADC0851/8 is automatically configured in the watch-
dog mode upon power-up. After reading the power fail bit
CS is pulled high. To exit the watchdog mode and to change
to a new mode of operation, CS should be high less than
eight oscillator clock periods for the ADC0851 and less than
thirty two oscillator clock periods for the ADC0858 respec-
tively (see the Timing Diagram, ‘‘Read Power Flag after
Power Up ADC0851/8’’). When changing to a new mode of
operation, the device readies itself to read a new input word
clocked in at the data input (DI) pin. The input word config-
ures the new mode of operation.
Functional Description
The simplified block diagram (Figure 1, front page) shows
the various functional blocks. The ADC0851 and ADC0858
include 2- and 8-channel analog input multiplexers respec-
tively. Using the appropriate serial input word at the Data
Input (DI) pin, the analog channels can be configured for
either single-ended operation or differential mode operation.
The COM input pin provides additional flexibility since the
COM pin functions as an inverting differential input common
to all analog inputs when each channel is configured as a
single ended channel. Applying an external DC voltage at
the COM pin allows offsetting the single ended analog input
voltages from ground (pseudo-differential mode). Input
channels that are configured as differential pairs will be un-
affected by the voltage at COM pin.
The ADC0851/8 includes an 8-bit DAC, a comparator and
an 8-bit successive approximation register. An analog-to-
digital conversion can be initiated at any time on any one of
the input channels. The 8-bit digital word corresponding to
the analog input voltage is serially clocked out at the Data
Output (DO) pin. In addition to its use as a multiplexed A/D
converter, the ADC0851/8 may also be used as a window
comparator in the watchdog mode. An upper and lower
boundary limit corresponding to each analog input voltage
may be stored in an internal RAM. The RAM consists of
sixteen memory locations, each 8 bit wide; however, for the
ADC0851 only four memory locations are used. Limit data
can either be written into or read back from the RAM. The
read/write capability allows independent software routines
to read back previously programmed window limits. Further-
more, currently programmed limits may also be read back to
ensure system testability. An address register holds the ad-
dresses of the RAM’s memory locations where data may
either be stored or retrieved from.
When the device is operated in the watchdog mode (as de-
scribed in the ‘‘general overview’’ section), the analog in-
puts are continually polled and compared against their re-
spective window limits. Once an input signal that has ex-
ceeded either boundary limit is detected, a ‘‘1’’ is stored in
the MSB position in a 16-bit status register, indicating a limit
crossing. Note that the ADC0851 uses only four locations of
the status register because it has only four limits. In addi-
tion, the tag register is updated so that the register holds the
address which indicates the channel and the corresponding
upper or lower limit that was crossed. After the first limit
crossing is detected, the device cycles through the remain-
ing limits and compares them against their respective input
signals. If any additional limit crossing is or are detected
then a ‘‘1’’ is stored in the appropriate locations of the
status register. After the completion of this operation, the
interrupt pin (INT) goes low, providing a flag to a microproc-
essor. The microprocessor can then cause the serial status
data to be shifted out by bringing the CS line low. Together
with the status and tag bits, the microprocessor can deter-
mine which channel exceeded which limit. If desired the mi-
16
相关PDF资料 |
PDF描述 |
|---|---|
| ADC0851 | 8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0851BIN | 8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0851BIV | 8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0851CIN | 8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0851CIV | 8-Bit Analog Data Acquisition and Monitoring Systems |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADC0858CIJ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| ADC0858CIN | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0858CIV | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0858CMJ/883 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| ADC0881 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit 20 MSPS Flash A/D Converter |
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