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参数资料
| 型号： | ADC0858CIV |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 8-Bit Analog Data Acquisition and Monitoring Systems |
| 中文描述： | 8-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20 |
| 封装： | PLASTIC, LCC-20 |
| 文件页数： | 14/36页 |
| 文件大小： | 581K |
| 代理商： | ADC0858CIV |
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General Overview
The ADC0851/58 is a versatile microprocessor-compatible
data acquisition system with an on-board watchdog capabili-
ty. The device is capable of synchronous serial interface
with most microprocessors and includes a multiplexer, a
RAM
and
a
successive
approximation
ADC0851 and the ADC0858 have two and eight input chan-
nels respectively.
register.
The
1.0 Modes of Operation
The device can be used in any one of the eight modes of
operation listed below. A mode is selected by taking CS low
and providing the IC with an input word whose first four bits
specify the desired mode (see the ‘‘Programming Charts’’
for the mode selection codes):
1.1 WATCHDOG MODE
This mode of operation allows the device to operate as a
digitally-programmable window comparator. The analog in-
put voltage at each channel is compared against the upper
and lower boundary limits stored in an internal RAM. When
an input falls outside of its programmed window limits, an
interrupt is generated. The microprocessor can then pull CS
low which causes the device to produce a bit stream that
indicates which channel(s) crossed which limit(s).
The watchdog mode is selected by taking CS low and shift-
ing in the four bit word (1 0 0 0) followed by a twelve bit
word that configures the analog inputs to operate either as
single-ended or as differential pairs (CH0–CH1, CH2–CH3,
etc.). When a channel is operating single-ended, its input
voltage is compared to the upper and lower limits stored in
RAM for that input. When two inputs are configured as a
differential pair, the limits stored in the RAM for the channel
with the lower number will be compared against the differ-
ential input voltage. For example, the differential voltage
CH0–CH1 will be compared with the lower and upper limits
for CH0. The limits are programmed using the ‘‘write one
limit to RAM’’ or ‘‘write all limits to RAM’’ mode.
Data Input (DI) WordDADC0851 or ADC0858
TL/H/11021–23
1.2 WRITE ONE LIMIT TO RAM
This mode allows the user to update a single limit for one of
the input channels. This is accomplished by using a 16-bit
stream of input data (see ‘‘Programming Chart’’). The first
four bits (1 0 0 1) select the mode, the next four bits select
the input channel and the limit (upper or lower) that will be
preset, and the last eight bits set the limit (or comparator
threshold).
The limit data representing the input voltage limit (or com-
parator threshold) is expressed as per the following equa-
tion:
V
LIM
e
V
REF
(
(/2
L7
a
(/4
L6
a
. . .
a
1
/
256 L0)
where L7 is the MSB.
Data Input (DI) WordDADC0851 or ADC0858
TL/H/11021–24
1.3 WRITE ALL LIMITS TO RAM
This mode is used to update each pair of lower and upper
limits for all channels. This is accomplished by a stream of
input data whose first four bits select the mode of operation
followed by four bytes of limit data for the ADC0851 and
sixteen bytes of limit data for the ADC0858.
The limit data representing the input voltage limit (or com-
parator threshold) is expressed as per the following equa-
tion:
V
LIM
e
V
REF
(
(/2
L7
a
(/4
L6
a
. . .
a
1
/
256 L0)
where L7 is the MSB.
Data Input (DI) WordDADC0851 or ADC0858
TL/H/11021–25
1.4 READ ONE LIMIT FROM RAM
When the ADC0851/8 is configured in this mode, the user
can read back an 8-bit limit word from the RAM memory
location pointed to by the limit address. An 8-bit input word
selects the mode (1 0 1 1) and the memory location to be
read.
Data Input (DI)DADC0851 or ADC0858
TL/H/11021–26
14
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