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| 型号： | ADCLK914BCPZ-WP |
| 厂商： | Analog Devices Inc |
| 文件页数： | 1/12页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA BUFF DVR 1:1 16LFCSP |
| 标准包装： | 50 |
| 系列： | SIGe |
| 类型： | 缓冲器/驱动器，数据 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:1 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | CML，CMOS，LVDS，LVPECL，LVTTL |
| 输出： | HVDS |
| 频率 - 最大： | 7.5GHz |
| 电源电压： | 2.97 V ~ 3.63 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ |
| 包装： | 托盘 - 晶粒 |
Ultrafast, SiGe, Open-Collector
HVDS Clock/Data Buffer
ADCLK914
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2008 Analog Devices, Inc. All rights reserved.
FEATURES
7.5 GHz operating frequency
160 ps propagation delay
100 ps output rise/fall
110 fs random jitter
On-chip input terminations
Extended industrial temperature range: 40°C to +125°C
3.3 V power supply (VCC VEE)
APPLICATIONS
Clock and data signal restoration
High speed converter clocking
Broadband communications
Cellular infrastructure
High speed line receivers
ATE and high performance instrumentation
Level shifting
Threshold detection
FUNCTIONAL BLOCK DIAGRAM
D
Q
VCC
VEE
VT
Q
D
Q
VCC
VEE
VT
Q
VREF
0656
1-
001
50
ADCLK914
Figure 1.
GENERAL DESCRIPTION
The ADCLK914 is an ultrafast clock/data buffer fabricated on
the Analog Devices, Inc., proprietary, complementary bipolar
(XFCB-3) silicon-germanium (SiGe) process. The ADCLK914
features high voltage differential signaling (HVDS) outputs
suitable for driving the latest Analog Devices high speed digital-
to-analog converters (DACs). The ADCLK914 has a single,
differential open-collector output.
The ADCLK914 buffer operates up to 7.5 GHz with a 160 ps
propagation delay and adds only 110 fs random jitter (RJ).
The input has a center tapped, 100 Ω, on-chip termination
resistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS
(ac-coupled only). A VREF pin is available for biasing ac-coupled
inputs.
The HVDS output stage is designed to directly drive 1.9 V each
side into 50 Ω terminated to VCC for a total differential output
swing of 3.8 V.
The ADCLK914 is available in a 16-lead LFCSP. It is specified
for operation over the extended industrial temperature range of
40°C to +125°C.
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