参数资料
型号: ADCLK950BCPZ-REEL7
厂商: Analog Devices Inc
文件页数: 1/12页
文件大小: 0K
描述: IC CLOCK BUFFER MUX 2:10 40LFCSP
标准包装: 750
系列: SIGe
类型: 扇出缓冲器(分配),多路复用器
电路数: 1
比率 - 输入:输出: 2:10
差分 - 输入:输出: 是/是
输入: CML,CMOS,LVDS,LVPECL
输出: LVPECL
频率 - 最大: 4.8GHz
电源电压: 2.97 V ~ 3.63 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-VQ(6x6)
包装: 带卷 (TR)
Two Selectable Inputs, 10 LVPECL Outputs,
SiGe Clock Fanout Buffer
ADCLK950
Rev. A
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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
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Tel: 781.329.4700
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Fax: 781.461.3113
2009–2010 Analog Devices, Inc. All rights reserved.
FEATURES
2 selectable differential inputs
4.8 GHz operating frequency
75 fs rms broadband random jitter
On-chip input terminations
3.3 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK950 is an ultrafast clock fanout buffer fabricated
on the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The ADCLK950 is an ultrafast clock fanout buffer fabricated
on the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
VREFx pin is available for biasing ac-coupled inputs.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
VREFx pin is available for biasing ac-coupled inputs.
The ADCLK950 features 10 full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The ADCLK950 features 10 full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to VCC 2 V for a total differential
output swing of 1.6 V.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to VCC 2 V for a total differential
output swing of 1.6 V.
The ADCLK950 is available in a 40-lead LFCSP and specified
for operation over the standard industrial temperature range of
40°C to +85°C.
The ADCLK950 is available in a 40-lead LFCSP and specified
for operation over the standard industrial temperature range of
40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
VT0
VREF0
VREF1
IN_SEL
CLK0
VT1
CLK1
LVPECL
ADCLK950
REFERENCE
08
27
9-
0
01
Figure 1.
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