参数资料
型号: ADCMP567BCPZ
厂商: Analog Devices Inc
文件页数: 15/17页
文件大小: 0K
描述: IC COMP DUAL ULTRA-FAST 32LFCSP
标准包装: 1
类型: 带锁销
元件数: 2
输出类型: 补充型,差分,开路发射极,PECL
电压 - 电源,单路/双路(±): ±4.75 V ~ 5.25 V
电压 - 输入偏移(最小值): 5mV @ 5V
电流 - 输入偏压(最小值): 24µA @ 5V
电流 - 输出(标准): 30mA
电流 - 静态(最大值): 20mA,95mA,18mA
CMRR, PSRR(标准): 69dB CMRR
传输延迟(最大): 0.3ns
磁滞: ±1mV
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘,CSP
安装类型: 表面贴装
包装: 托盘
产品目录页面: 764 (CN2011-ZH PDF)
配用: EVAL-ADCMP567BCPZ-ND - BOARD EVALUATION ADCMP567BCP
ADCMP567
Rev. 0 | Page 7 of 16
Pin No.
Mnemonic
Function
22
VEE
Negative Supply Terminal
23
NC
No Connect. Leave pin unconnected.
24
VEE
Negative Supply Terminal
25
VDD
Logic Supply Terminal
26
QA
One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 30) for more information.
27
QA
One of two complementary outputs for Channel A. QA will be at logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 30) for more information.
28
VDD
Logic Supply Terminal
29
NC
No Connect. Leave pin unconnected.
30
LEA
One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven
in conjunction with LEA.
31
LEA
One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the
output will track changes at the input of the comparator. In the latch mode (logic high), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven
in conjunction with LEA.
32
GND
Analog Ground
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