- 您现在的位置：买卖IC网 > PDF目录10735 > ADCMP581BCPZ-WP (Analog Devices Inc)IC COMPARATOR ECL UFAST 16-LFCSP PDF资料下载
参数资料
| 型号： | ADCMP581BCPZ-WP |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC COMPARATOR ECL UFAST 16-LFCSP |
| 标准包装： | 50 |
| 类型： | 带锁销 |
| 元件数： | 1 |
| 输出类型： | 补充型，ECL |
| 电压 - 电源，单路/双路(±)： | ±4.5 V ~ 5.5 V |
| 电压 - 输入偏移（最小值）： | 10mV @ ±5V |
| 电流 - 输入偏压（最小值）： | 30µA @ ±5V |
| 电流 - 输出（标准）： | 44mA @ 5V |
| 电流 - 静态（最大值）： | 8mA |
| CMRR, PSRR（标准）： | 60dB CMRR，75dB PSRR |
| 传输延迟（最大）： | 0.18ns |
| 磁滞： | 1mV |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 安装类型： | 表面贴装 |
| 包装： | 托盘 - 晶粒 |
| 配用： | EVAL-ADCMP581BCPZ-ND - BOARD EVALUATION ADCMP581BCP |
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 5 of 16
TIMING INFORMATION
Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the
terms shown in Figure 2.
50%
VN ± VOS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
LATCH ENABLE
tH
tPDL
tPDH
tPLOH
tPLOL
tR
tF
VN
VOD
tS
tPL
04672-028
Figure 2. Comparator Timing Diagram
Table 2. Timing Descriptions
Symbol
Timing
Description
tPDH
Input-to-Output High Delay
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output low-to-high transition.
tPDL
Input-to-Output Low Delay
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output high-to-low transition.
tPLOH
Latch Enable-to-Output High Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
tPLOL
Latch Enable-to-Output Low Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
tH
Minimum Hold Time
Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
tPL
Minimum Latch Enable Pulse Width
Minimum time that the latch enable signal must be high to acquire an input signal change.
tS
Minimum Setup Time
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
tR
Output Rise Time
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
tF
Output Fall Time
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
VN
Normal Input Voltage
Difference between the input voltages VP and VN for output true.
VOD
Voltage Overdrive
Difference between the input voltages VP and VN for output false.
相关PDF资料 |
PDF描述 |
|---|---|
| ADCMP582BCPZ-WP | IC COMPARATOR PECL UFAST 16LFCSP |
| ADCMP572BCPZ-WP | IC COMPARATOR CML 3.3-5V 16LFCSP |
| VE-J4V-MY-F4 | CONVERTER MOD DC/DC 5.8V 50W |
| VI-JNW-MY-F2 | CONVERTER MOD DC/DC 5.5V 50W |
| VE-2WN-MY-B1 | CONVERTER MOD DC/DC 18.5V 50W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADCMP582 | 制造商:AD 制造商全称:Analog Devices 功能描述:Ultrafast SiGe Voltage Comparator |
| ADCMP582BCP | 制造商:Analog Devices 功能描述:COMPARATOR SGL 5.5V 16LFCSP EP - Bulk |
| ADCMP582BCP-R2 | 制造商:Analog Devices 功能描述:Comparator Single ±5.5V 16-Pin LFCSP EP T/R 制造商:Rochester Electronics LLC 功能描述:DUAL SUPPLY, PECL ON XFCB3.0 - Bulk |
| ADCMP582BCP-RL7 | 制造商:Analog Devices 功能描述:Comparator Single ±5.5V 16-Pin LFCSP EP T/R |
| ADCMP582BCP-WP | 制造商:Analog Devices 功能描述:Comparator Single ±5.5V 16-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
发布紧急采购，3分钟左右您将得到回复。