参数资料
型号: ADCMP582BCPZ-R2
厂商: Analog Devices Inc
文件页数: 1/16页
文件大小: 0K
描述: IC COMPARATOR PECL UFAST 16LFCSP
标准包装: 1
类型: 带锁销
元件数: 1
输出类型: 补充型,PECL
电压 - 电源,单路/双路(±): ±4.5 V ~ 5.5 V
电压 - 输入偏移(最小值): 10mV @ ±5V
电流 - 输入偏压(最小值): 30µA @ ±5V
电流 - 输出(标准): 44mA @ 5V
电流 - 静态(最大值): 8mA
CMRR, PSRR(标准): 60dB CMRR,75dB PSRR
传输延迟(最大): 0.18ns
磁滞: 1mV
工作温度: -40°C ~ 125°C
封装/外壳: 16-VFQFN 裸露焊盘,CSP
安装类型: 表面贴装
包装: 标准包装
产品目录页面: 765 (CN2011-ZH PDF)
配用: EVAL-ADCMP582BCPZ-ND - BOARD EVALUATION ADCMP582BCP
其它名称: ADCMP582BCPZ-R2DKR
Ultrafast SiGe
Voltage Comparators
ADCMP580/ADCMP581/ADCMP582
Rev. A
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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
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2005–2007 Analog Devices, Inc. All rights reserved.
FEATURES
180 ps propagation delay
25 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
100 ps minimum pulse width
37 ps typical output rise/fall
10 ps deterministic jitter (DJ)
200 fs random jitter (RJ)
2 V to +3 V input range with +5 V/5 V supplies
On-chip terminations at both input pins
Resistor-programmable hysteresis
Differential latch control
Power supply rejection > 70 dB
APPLICATIONS
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Clock and data signal restoration
FUNCTIONAL BLOCK DIAGRAM
VP NONINVERTING
INPUT
VTP TERMINATION
VCCI
VCCO
VEE
VTN TERMINATION
VN INVERTING
INPUT
LE INPUT
HYS
Q OUTPUT
LE INPUT
ADCMP580/
ADCMP581/
ADCMP582
CML/ECL/
PECL
0
467
2-
0
01
Figure 1.
GENERAL DESCRIPTION
The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage
comparators fabricated on the Analog Devices, Inc. proprietary
XFCB3 Silicon Germanium (SiGe) bipolar process. The
ADCMP580 features CML output drivers, the ADCMP581
features reduced swing ECL (negative ECL) output drivers, and
the ADCMP582 features reduced swing PECL (positive ECL)
output drivers.
All three comparators offer 180 ps propagation delay and 100 ps
minimum pulse width for 10 Gbps operation with 200 fs random
jitter (RJ). Overdrive and slew rate dispersion are typically less
than 15 ps.
The ±5 V power supplies enable a wide 2 V to +3 V input
range with logic levels referenced to the CML/NECL/PECL
outputs. The inputs have 50 Ω on-chip termination resistors
with the optional capability to be left open (on an individual
pin basis) for applications requiring high impedance input.
The CML output stage is designed to directly drive 400 mV into
50 Ω transmission lines terminated to ground. The NECL output
stages are designed to directly drive 400 mV into 50 Ω terminated
to 2 V. The PECL output stages are designed to directly drive
400 mV into 50 Ω terminated to VCCO 2 V. High speed latch
and programmable hysteresis are also provided. The differential
latch input controls are also 50 Ω terminated to an independent
VTT pin to interface to either CML or ECL or to PECL logic.
The ADCMP580/ADCMP581/ADCMP582 are available in a
16-lead LFCSP_VQ.
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