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| 型号： | ADCMP604BKSZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/16页 |
| 文件大小： | 0K |
| 描述： | IC COMP TTL/CMOS 1CHAN SC70-6 |
| 标准包装： | 10,000 |
| 类型： | 通用 |
| 元件数： | 1 |
| 输出类型： | 补充型，LVDS，满摆幅 |
| 电压 - 电源，单路/双路(±)： | 2.5 V ~ 5.5 V |
| 电压 - 输入偏移（最小值）： | 5mV @ 3V |
| 电流 - 输入偏压（最小值）： | 5µA @ 3V |
| 电流 - 输出（标准）： | 50mA |
| 电流 - 静态（最大值）： | 21mA |
| CMRR, PSRR（标准）： | 50dB CMRR，50dB PSRR |
| 传输延迟（最大）： | 3ns |
| 磁滞： | 100µV |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 6-TSSOP，SC-88，SOT-363 |
| 安装类型： | 表面贴装 |
| 包装： | 带卷 (TR) |
ADCMP604/ADCMP605
Rev. A | Page 10 of 16
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP604/ADCMP605 comparators are very high speed
devices. Despite the low noise output stage, it is essential to use
proper high speed design techniques to achieve the specified
performance. Because comparators are uncompensated amplifiers,
feedback in any phase relationship is likely to cause oscillations
or undesired hysteresis. The use of low impedance supply
planes is of critical importance particularly the output supply
plane (VCCO) and the ground plane (GND). Individual supply
planes are recommended as part of a multilayer board.
Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.
It is also important to adequately bypass the input and output
supplies. Multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the VCCI and VCCO supply
pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the VCCI pin and the VCCO pin. High frequency bypass capacitors
should be carefully selected for minimum inductance and ESR.
Parasitic layout inductance should also be strictly controlled to
maximize the effectiveness of the bypass at high frequencies.
If the package allows, and the input and output supplies have
been connected separately (VCCI ≠ VCCO), be sure to bypass each
of these supplies separately to the GND plane. Do not connect a
bypass capacitor between these supplies. It is recommended that
the GND plane separate the VCCI and VCCO planes when the
circuit board layout is designed to minimize coupling between
the two supplies to take advantage of the additional bypass
capacitance from each respective supply to the ground plane.
This enhances the performance when split input/output supplies
are used. If the input and output supplies are connected together
for single-supply operation (VCCI = VCCO), coupling between the
two supplies is unavoidable; however, careful board placement
can help keep output return currents away from the inputs.
LVDS-COMPATIBLE OUTPUT STAGE
Specified propagation delay dispersion performance is only
achieved by keeping parasitic capacitive loads at or below the
specified minimums. The outputs of the ADCMP604 and
ADCMP605 are designed to directly drive any standard LVDS-
compatible input.
USING/DISABLING THE LATCH FEATURE
The latch input is designed for maximum versatility. It can
safely be left floating or it can be driven low by any standard
TTL/CMOS device as a high speed latch. In addition, the pin
can be operated as a hysteresis control pin with a bias voltage of
1.25 V nominal and an input resistance of approximately
70 kΩ. This allows the comparator hysteresis to be easily
controlled by either a resistor or an inexpensive CMOS DAC.
Driving this pin high or floating the pin disables all hysteresis.
Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected in
parallel to the hysteresis control resistor or current source.
Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V, regardless of VCCO.
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and often cause oscillation. Large discontinuities along input
and output transmission lines can also limit the specified pulse-
width dispersion performance. The source impedance should
be minimized as much as is practicable. High source impedance,
in combination with the parasitic input capacitance of the
comparator, causes an undesirable degradation in bandwidth at
the input, thus degrading the overall response. Thermal noise
from large resistances can easily cause extra jitter with slowly
slewing input signals. Higher impedances encourage undesired
coupling.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADCMP604BKSZ-RL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators |
| ADCMP605 | 制造商:AD 制造商全称:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators |
| ADCMP605BCPZ-R2 | 功能描述:IC COMP TTL/CMOS 1CHAN 12-LFCSP RoHS:是 类别:集成电路 (IC) >> 线性 - 比较器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
| ADCMP605BCPZ-R21 | 制造商:AD 制造商全称:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators |
| ADCMP605BCPZ-R7 | 功能描述:IC COMP TTL/CMOS 1CHAN 12-LFCSP RoHS:是 类别:集成电路 (IC) >> 线性 - 比较器 系列:- 标准包装:1 系列:- 类型:通用 元件数:1 输出类型:CMOS，开路集电极，TTL 电压 - 电源，单路/双路(±):2.7 V ~ 5.5 V 电压 - 输入偏移（最小值）:7mV @ 5V 电流 - 输入偏压（最小值）:0.25µA @ 5V 电流 - 输出（标准）:84mA @ 5V 电流 - 静态（最大值）:120µA CMRR, PSRR（标准）:- 传输延迟（最大）:600ns 磁滞:- 工作温度:-40°C ~ 85°C 封装/外壳:SC-74A，SOT-753 安装类型:表面贴装 包装:剪切带 (CT) 产品目录页面:1268 (CN2011-ZH PDF) 其它名称:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
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