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参数资料
| 型号： | ADD5203ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | IC LED DRVR WHITE BCKLGT 28LFCSP |
| 标准包装： | 1 |
| 恒定电流： | 是 |
| 拓扑： | PWM，升压（升压） |
| 输出数： | 8 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光 |
| 类型 - 次要： | 白色 LED |
| 频率： | 350kHz ~ 1MHz |
| 电源电压： | 6 V ~ 21 V |
| 输出电压： | 45V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 28-LFCSP-WQ（4x4） |
| 包装： | 标准包装 |
| 工作温度： | -25°C ~ 85°C |
| 其它名称： | ADD5203ACPZ-RLDKR |
ADD5203
SMBUS REGISTER DESCRIPTION
The ADD5203 has four registers to control and monitor
brightness, fault status, identifications, and operating mode.
Those registers are one byte wide and accessible via the SMBus
read/write byte protocols.
Brightness Control Register (Address 0x00)
This register consists of eight bits, BRT7 to BRT0, which are used
to control the LED brightness level in 256 steps. An SMBus write
byte cycle to this register sets the brightness level if the device is
in SMBus mode. In addition, a write byte cycle to this register sets
the brightness level if the device is in SMBus mode. Furthermore,
a write byte cycle to this register has no effect when the device is
in a mode other than SMBus mode. The operating mode is
selected by the device control register (Address 0x01).
An SMBus read byte cycle to this register returns the current
brightness level, regardless of the value of PWM_SEL. An SMBus
setting of 0xFF for this register sets the device to the maximum
brightness output, and a setting of 0x00 sets the device to the
minimum brightness output.
This register is both readable and writable for all bits. The default
value is 0xFF.
Device Control Register (Address 0x01)
This register has three bits. Two bits control the operation mode
of the device, and a single bit controls the backlight on/off state.
This register is both readable and writable for Bit 0 to Bit 2. Bit 0,
named BL_CTL, is used as on/off control for the output LEDs.
Bit 1 and Bit 2, named PWM_SEL and PWM_MD, control the
The PWM_MD bit selects the manner in which the PWM input is to
be interpreted. When this bit is 0, the PWM input reflects a percent
change in the current brightness (that is, DPST mode) and should be
as follows:
DPST Brightness = C BT × (PWM)
where:
C BT is the current brightness setting from SMBus without influence
from the PWM.
PWM is the percent duty cycle.
The PWM signal starts from 100% when operating in DPST mode.
When PWM_MD is 1, the PWM input has no effect on the
brightness setting, unless the ADD5203 is in PWM mode. In
addition, when operating in PWM mode, this bit is a do not care (see
Table 10). The PWM_SEL bit determines whether the SMBus or
PWM input should drive brightness.
The relationship between these two control bits can be thought of as
specifying an operating mode for the ADD5203. The defined modes
are shown in Table 10. Note that depending on the setting of some
bits, other bits have no effect and are do not cares, shown as X
in Table 10.
Table 10. Operating Modes Selected by Device Control
Register Bit 1 and Bit 2
PWM_SEL (Bit 1) PWM_MD 1 (Bit 2) Mode
1 X PWM mode
0 1 SMBus mode
0 0 SMBus mode with DPST
operating mode of the device, respectively. If the BL_CRT bit is
1
X is don’t care.
set to 1, the device turns on the backlight within 10 ms after the
write cycle. If the BL_CRT bit is set to 0, the device turns off the
backlight immediately. The ADD5203 output operating mode is
selected by the combination of Bit 1 and Bit 2 (see Table 10).
Table 11. Brightness Control Register (Address 0x00) Bit Map
MSB
All reserved bits return to 0 when read, and the bits are ignored when
written. This default value of the register is 0x00.
LSB
Bit 7 (R/W)
BRT7
Bit 6 (R/W)
BRT6
Bit 5 (R/W)
BRT5
Bit 4 (R/W)
BRT4
Bit 3 (R/W)
BRT3
Bit 2 (R/W)
BRT2
Bit 1 (R/W)
BRT1
Bit 0 (R/W)
BRT0
Default Value
0xFF
Table 12. Brightness Control Register (Address 0x00) Bit Description
Bit Name
BRT[7:0]
Description
256 steps of brightness levels
Table 13. Device Control Register (Address 0x01) Bit Map
MSB
LSB
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2 (R/W)
PWM_MD
Bit 1 (R/W)
PWM_SEL
Bit 0 (R/W)
BL_CTL
Default Value
0x00
Rev. 0 | Page 15 of 24
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