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参数资料
| 型号： | ADE5169ASTZF62 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 146/156页 |
| 文件大小： | 0K |
| 描述： | IC METER/8052/RTC/LCD DR 64LQFP |
| 标准包装： | 1 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 产品目录页面： | 797 (CN2011-ZH PDF) |
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ADE5166/ADE5169/ADE5566/ADE5569
I 2 C-COMPATIBLE INTERFACE
The ADE5166/ADE5169/ADE5566/ADE5569 support a fully
licensed I 2 C interface. The I 2 C interface is implemented as a full
Data Sheet
The bit rate is defined in the I2CMOD SFR (Address 0xE8)
as follows:
hardware master.
SDATA (P0.4/MOSI/SDATA) is the data I/O pin, and SCLK
f SCLK =
f CORE
16 × 2 I 2 CR [ 1 : 0 ]
(P0.6/SCLK/T0) is the serial clock. These two pins are shared with
the MOSI and SCLK pins of the on-chip SPI interface. Therefore,
the user can enable only one interface at a time on these pins. The
SCPS bit in the configuration SFR (CFG, Address 0xAF[5]) selects
which peripheral is active.
The two pins used for data transfer, SDATA and SCLK, are
configured in a wire-AND format that allows arbitration in a
SLAVE ADDRESSES
The I 2 C slave address SFR (I2CADR, Address 0xE9) contains
the slave device ID. The LSB of this register contains a read/write
request. A write to this SFR starts the I 2 C communication.
I 2 C REGISTERS
The I 2 C peripheral interface consists of five SFRs.
multimaster system.
?
I2CMOD
The transfer sequence of an I C system consists of a master device
2
initiating a transfer by generating a start condition while the bus
is idle. The master transmits the address of the slave device and
the direction of the data transfer in the initial address transfer. If
the slave acknowledges, the data transfer is initiated. This continues
until the master issues a stop condition and the bus becomes idle.
SERIAL CLOCK GENERATION
The I 2 C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (256 kHz) or in standard mode (32 kHz).
Table 156. I 2 C SFR List
? SPI2CSTAT
? I2CADR
? SPI2CTx
? SPI2CRx
Because the SPI and I 2 C serial interfaces share the same pins,
they also share the same SFRs, such as the SPI2CTx and SPI2CRx
SFRs. In addition, the I2CMOD, I2CADR, and SPI2CSTAT SFRs
are shared with the SPIMOD1, SPIMOD2, and SPISTAT SFRs,
respectively.
SFR Address
0x9A
0x9B
0xE8
0xE9
0xEA
Mnemonic
SPI2CTx
SPI2CRx
I2CMOD
I2CADR
SPI2CSTAT
R/W
W
R
R/W
R/W
R/W
Length
8
8
8
8
8
Default
0
0
0
0
Description
SPI/I 2 C transmit buffer (see Table 151).
SPI/I 2 C receive buffer (see Table 152).
I 2 C mode (see Table 157).
I 2 C slave address (see Table 158).
I 2 C interrupt status (see Table 159).
Table 157. I 2 C Mode SFR (I2CMOD, Address 0xE8)
Bit
7
Bit Address
0xEF
Mnemonic
I2CEN
Default
0
Description
I 2 C enable bit. When this bit is set to Logic 1, the I 2 C interface is enabled. A write to the
I2CADR SFR (Address 0xE9) starts a communication.
[6:5]
0xEE to 0xED
I2CR
00
I 2 C SCLK frequency.
I2CR
00
01
10
11
Result
f CORE /16 = 256 kHz if f CORE = 4.096 MHz
f CORE /32 = 128 kHz if f CORE = 4.096 MHz
f CORE /64 = 64 kHz if f CORE = 4.096 MHz
f CORE /128 = 32 kHz if f CORE = 4.096 MHz
[4:0]
0xEC to 0xE8
I2CRCT
00000
Configures the length of the I 2 C received FIFO buffer. The I 2 C peripheral stops when
I2CRCT[4:0] + 1 byte have been read, or if an error occurs.
Table 158. I 2 C Slave Address SFR (I2CADR, Address 0xE9)
Bit
[7:1]
0
Mnemonic
I2CSLVADR
I2CR_W
Default
0
0
Description
Address of the I 2 C slave being addressed. Writing to this register starts the I 2 C transmission (read or write).
Command bit for read or write. When this bit is set to Logic 1, a read command is transmitted on the
I 2 C bus. Data from the slave in the SPI2CRx SFR (Address 0x9B) is expected after a command byte.
When this bit is set to Logic 0, a write command is transmitted on the I 2 C bus. Data to the slave is
expected in the SPI2CTx SFR.
Rev. D | Page 146 of 156
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