参数资料
| 型号： | ADE7166ASTZF8 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 140/152页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 1PHASE 64LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 160 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Table 154. I 2 C Interrupt Status Register SFR (SPI2CSTAT, Address 0xEA)
Bit
7
6
Mnemonic
I2CBUSY
I2CNOACK
Default
0
0
Description
This bit is set to Logic 1 when the I 2 C interface is used. When set, the Tx FIFO is emptied.
I 2 C no acknowledgement transmit interrupt. This bit is set to Logic 1 when the slave device
does not send an acknowledgement. The I 2 C communication is stopped after this event.
Write a 0 to this bit to clear it.
5
I2CRxIRQ
0
I 2 C receive interrupt. This bit is set to Logic 1 when the receive FIFO is not empty.
Write a 0 to this bit to clear it.
4
I2CTxIRQ
0
I 2 C Transmit Interrupt. This bit is set to Logic 1 when the transmit FIFO is empty.
Write a 0 to this bit to clear it.
[3:2]
I2CFIFOSTAT
0
Status bits for 3- or 4-bytes deep I 2 C FIFO. The FIFO monitored in these two bits is the one currently
used in I 2 C communication (receive or transmit) because only one FIFO is active at a time.
I2CFIFOSTAT
00
01
10
11
Result
FIFO empty
Reserved
FIFO half full
FIFO full
1
0
I2CACC_ERR
I2CTxWR_ERR
0
0
Set when trying to write and read at the same time. Write a 0 to this bit to clear it.
Set when a write was attempted when the I 2 C transmit FIFO was full. Write a 0 to this bit to clear it.
READ AND WRITE OPERATIONS
1
9
1
9
1
9
SCLK
SDATA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK BY
SLAVE
FRAME 2
DATA BYTE 1 FROM MASTER
ACK BY
MASTER
FRAME N + 1
DATA BYTE N FROM SLAVE
NACK BY STOP BY
MASTER MASTER
Figure 113. I 2 C Read Operation
1
9
1
9
SCLK
SDATA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK BY
SLAVE
FRAME 2
DATA BYTE 1 FROM MASTER
ACK BY
SLAVE
STOP BY
MASTER
Figure 114. I 2 C Write Operation
Figure 113 and Figure 114 depict I 2 C read and write operations,
respectively. Note that the LSB of the I2CADR SFR is used to
select whether a read or write operation is performed on the
slave device. During the read operation, the master acknowledges
are generated automatically by the I 2 C peripheral. The master
generated NACK (no acknowledge) before the end of a read
operation is also automatically generated after the I2CRCT bits
have been read from the slave. If the I2CADR register is
updated during a transmission, instead of generating a stop at
Reading the SPI/I 2 C Receive Buffer SFR (SPI2CRx,
Address 0x9B)
Reading the SPI2CRx SFR should be done with a 2-cycle
instruction, such as
Mov a, spi2crx or Mov R0, spi2crx.
A 3-cycle instruction such as
Mov 3dh, spi2crx
does not transfer the right data into RAM Address 0x3D.
the end of the read or write operation, the master generates a
start condition and continues with the next communication.
Rev. B | Page 140 of 1 52
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