参数资料
| 型号： | ADE7166ASTZF8 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 48/152页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 1PHASE 64LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 160 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Table 41. Interrupt Status 2 SFR (MIRQSTM, Address 0xDD)
Bit
7
6
5
4
3
2
1
0
Interrupt Flag
CF2
CF1
VAEOF
REOF 1
AEOF
VAEHF
REHF 1
AEHF
Description
Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if the CF2 pulse output is not
enabled by clearing Bit 2 of the MODE1 register.
Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if the CF1 pulse output is not
enabled by clearing Bit 1 of the MODE1 register.
Logic 1 indicates that the VAHR register has overflowed.
Logic 1 indicates that the VARHR register has overflowed.
Logic 1 indicates that the WATTHR register has overflowed.
Logic 1 indicates that the VAHR register is half full.
Logic 1 indicates that the VARHR register is half full.
Logic 1 indicates that the WATTHR register is half full.
1
This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
Table 42. Interrupt Status 3 SFR (MIRQSTH, Address 0xDE)
Bit
7
6
5
4
3
2
1
0
Interrupt Flag
RESET
Reserved
WFSM
PKI
PKV
CYCEND
ZXTO
ZX
Description
Indicates the end of a reset (for both software and hardware reset).
Reserved.
Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7).
Logic 1 indicates that the current channel has exceeded the IPKLVL value.
Logic 1 indicates that the voltage channel has exceeded the VPKLVL value.
Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles.
Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles.
Logic 1 indicates detection of a zero crossing in the voltage channel.
Table 43. Interrupt Enable 1 SF R (MIRQENL, Address 0xD9)
Bit
[7:6]
5
4
3
2
1
0
Interrupt Enable Bit
Reserved
FAULTSIGN 1
VARSIGN 2
APSIGN
VANOLOAD
RNOLOAD 2
APNOLOAD
Description
Reserved.
When this bit is set to Logic 1, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the APSIGN flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
1
2
This function is not available in the ADE7566 or ADE7569.
This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
Table 44. Interrupt Enable 2 SFR (MIRQENM, Address 0xDA)
Bit
7
6
5
4
3
2
1
0
Interrupt Enable Bit
CF2
CF1
VAEOF
REOF 1
AEOF
VAEHF
REHF 1
AEHF
Description
When this bit is set to Logic 1, a CF2 pulse creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, a CF1 pulse creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the REOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the AEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the REHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
1
This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
Rev. B | Page 48 of 152
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