参数资料
型号: ADE7758ARWZRL
厂商: Analog Devices Inc
文件页数: 66/72页
文件大小: 0K
描述: IC ENERGY METERING 3PHASE 24SOIC
标准包装: 1,000
输入阻抗: 380 千欧
测量误差: 0.1%
电压 - 高输入/输出: 2.4V
电压 - 低输入/输出: 0.8V
电流 - 电源: 8mA
电源电压: 4.75 V ~ 5.25 V
测量仪表类型: 3 相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 带卷 (TR)
ADE7758
Data Sheet
COMPUTATIONAL MODE REGISTER (0x16)
The computational method of the ADE7758 is defined by writing to the COMPMODE register. Table 21 summarizes the functionality of
each bit in the COMPMODE register.
Table 21. COMPMODE Register
Bit
Bit
Default
Location
0 to 1
Mnemonic
CONSEL
Value
0
Description
These bits are used t o select the input to the energy accumulation registers. CONSEL[1:0] = 11 is
reserved. IA, IB, and IC are IA, IB, and IC phase shifted by –90°, respectively.
Registers
AWATTHR
BWATTHR
CWATTHR
AVARHR
BVARHR
CVARHR
AVAHR
BVAHR
CVAHR
CONSEL[1, 0] = 00
VA × IA
VB × IB
VC × IC
VA × IA
VB × IB
VC × IC
VA RMS × IA RMS
VB RMS × IB RMS
VC RMS × IC RMS
CONSEL[1, 0] = 01
VA × (IA – IB)
0
VC × (IC – IB)
VA × (IA – IB)
0
VC × (IC – IB)
VA RMS × IA RMS
(VA RMS + VC RMS )/2 × IB RMS
VC RMS × IC RMS
CONSEL[1, 0] = 10
VA × (IA–IB)
0
VC × IC
VA × (IA–IB)
0
VC × IC
VA RMS × A RMS
VA RMS × IB RMS
VC RMS × IC RMS
2 to 4
TERMSEL
7
These bits are used to select the phases to be included in the APCF and VARCF pulse outputs. Setting
Bit 2 selects Phase A (the inputs to AWATTHR and AVARHR registers) to be included. Bit 3 and Bit 4
are for Phase B and Phase C, respectively. Setting all three bits enables the sum of all three phases to
be included in the frequency outputs (see the Active Power Frequency Output and the Reactive
Power Frequency Output sections).
5
ABS
0
Setting this bit places the APCF output pin in absolute only mode. Namely, the APCF output
frequency is proportional to the sum of the absolute values of the watt-hour accumulation registers
(AWATTHR, BWATTHR, and CWATTHR). Note that this bit only affects the APCF pin and has no effect
on the content of the corresponding registers.
6
SAVAR
0
Setting this bit places the VARCF output pin in the signed adjusted mode. Namely, the VARCF output
frequency is proportional to the sign-adjusted sum of the VAR-hour accumulation registers (AVARHR,
BVARHR, and CVARHR). The sign of the VAR is determined from the sign of the watt calculation from
the corresponding phase, that is, the sign of the VAR is flipped if the sign of the watt is negative, and
if the watt is positive, there is no change to the sign of the VAR. Note that this bit only affects the
VARCF pin and has no effect on the content of the corresponding registers.
7
NOLOAD
0
Setting this bit activates the no-load threshold in the ADE7758 .
Rev. E | Page 66 of 72
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