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| 型号： | ADE7759ARSRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/36页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 1PHASE 20SSOP |
| 标准包装： | 1,500 |
| 输入阻抗： | 390 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2.4V |
| 电压 - 低输入/输出： | 0.8V |
| 电流 - 电源： | 3mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-ADE7759EBZ-ND - BOARD EVALUATION FOR ADE7759 |
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ADE7759
TIMING CHARACTERISTICS 1, 2
(AV DD = DV DD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz
XTAL, T MIN to T MAX = –40 C to +85 C, unless otherwise noted.)
Parameter
A, B Versions
Unit
Test Conditions/Comments
Write Timing
t 1
t 2
t 3
t 4
t 5
t 6
t 7
t 8
Read Timing
t 9
t 10
t 113
20
150
150
10
5
6.4
4
100
4
4
30
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
m s (min)
m s (min)
ns (min)
m s (min)
m s (min)
ns (min)
CS Falling Edge to First SCLK Falling Edge
SCLK Logic High Pulsewidth
SCLK Logic Low Pulsewidth
Valid Data Setup Time before Falling Edge of SCLK
Data Hold Time after SCLK Falling Edge
Minimum Time between the End of Data Byte Transfers
Minimum Time between Byte Transfers during a Serial Write
CS Hold Time after SCLK Falling Edge
Minimum Time between Read Command (i.e., a Write to Communications
Register) and Data Read
Minimum Time between Data Byte Transfers during a Multibyte Read
Data Access Time after SCLK Rising Edge following a Write to the Communica-
tions Register
t 124
t 134
100
10
100
10
ns (max)
ns (min)
ns (max)
ns (min)
Bus Relinquish Time after Falling Edge of SCLK
Bus Relinquish Time after Rising Edge of CS
NOTES
1
2
3
4
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.
See Figures 2 and 3 and Serial Interface section of this data sheet.
Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
TO
200 A
I OL
OUTPUT
PIN
C L
50pF
1.6mA
I OH
2.1V
Figure 1. Load Circuit for Timing Specifications
t 8
CS
SCLK
t 1
t 2
t 3
t 7
t 7
t 6
t 4
t 5
DIN
1
0
0
A4
A3
A2
A1
A0
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
Figure 2. Serial Write Timing
CS
SCLK
t 1
t 9
t 10
t 13
DIN
0
0
0
A4
A3
A2
A1
A0
t 11
t 11
t 12
DOUT
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
Figure 3. Serial Read Timing
REV. A
–5 –
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