参数资料
型号: ADE7953ACPZ-RL
厂商: Analog Devices Inc
文件页数: 62/72页
文件大小: 0K
描述: IC ENERGY METERING 1PH 28LFCSP
标准包装: 5,000
输入阻抗: 660 千欧
测量误差: 0.1%
电压 - 高输入/输出: 2.4V
电压 - 低输入/输出: 0.4V
电流 - 电源: 6.8mA
电源电压: 3 V ~ 3.6 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘,CSP
供应商设备封装: 28-LFCSP-WQ(5x5)
包装: 带卷 (TR)
ADE7953
Address
Data Sheet
24-Bit
0x28C
0x28D
0x28E
0x28F
0x290
0x291
0x292
0x293
0x294
0x295
0x296
0x297
0x2FF
32-Bit
0x38C
0x38D
0x38E
0x38F
0x390
0x391
0x392
0x393
0x394
0x395
0x396
0x397
0x3FF
Register Name
BIGAIN
BVGAIN
BWGAIN
BVARGAIN
BVAGAIN
Reserved
BIRMSOS
Reserved
Reserved
BWATTOS
BVAROS
BVAOS
LAST_RWDATA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Default
0x400000
0x400000
0x400000
0x400000
0x400000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
Type
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Signed
Signed
Unsigned
Unsigned
Signed
Signed
Signed
Unsigned
Register Description
Current channel gain (Current Channel B)
This register should not be modified.
Active power gain (Current Channel B)
Reactive power gain (Current Channel B)
Apparent power gain (Current Channel B)
This register should not be modified.
IRMS offset (Current Channel B)
This register should not be modified.
This register should not be modified.
Active power offset correction (Current Channel B)
Reactive power offset correction (Current Channel B)
Apparent power offset correction (Current Channel B)
Contains the data from the last successful 24-bit/32-bit
register communication
ADE7953 REGISTER DESCRIPTIONS
Table 16. DISNOLOAD Register (Address 0x001)
Bits
0
1
2
Bit Name
DIS_APNLOAD
DIS_VARNLOAD
DIS_VANLOAD
Default
0
0
0
Description
1 = disable the active power no-load feature on Current Channel A and Current Channel B
1 = disable the reactive power no-load feature on Current Channel A and Current Channel B
1 = disable the apparent power no-load feature on Current Channel A and Current Channel B
Table 17. LCYCMODE Register (Address 0x004)
Bits
0
Bit Name
ALWATT
Default
0
Description
0 = disable active energy line cycle accumulation mode on Current Channel A
1 = enable active energy line cycle accumulation mode on Current Channel A
1
BLWATT
0
0 = disable active energy line cycle accumulation mode on Current Channel B
1 = enable active energy line cycle accumulation mode on Current Channel B
2
ALVAR
0
0 = disable reactive energy line cycle accumulation mode on Current Channel A
1 = enable reactive energy line cycle accumulation mode on Current Channel A
3
BLVAR
0
0 = disable reactive energy line cycle accumulation mode on Current Channel B
1 = enable reactive energy line cycle accumulation mode on Current Channel B
4
ALVA
0
0 = disable apparent energy line cycle accumulation mode on Current Channel A
1 = enable apparent energy line cycle accumulation mode on Current Channel A
5
BLVA
0
0 = disable apparent energy line cycle accumulation mode on Current Channel B
1 = enable apparent energy line cycle accumulation mode on Current Channel B
6
RSTREAD
1
0 = disable read with reset for all registers
1 = enable read with reset for all registers
Table 18. CONFIG Register (Address 0x102)
Bits
0
1
2
3
Bit Name
INTENA
INTENB
HPFEN
PFMODE
Default
0
0
1
0
Description
1 = integrator enable (Current Channel A)
1 = integrator enable (Current Channel B)
1 = HPF enable (all channels)
0 = power factor is based on instantaneous powers
1 = power factor is based on line cycle accumulation mode energies
4
REVP_CF
0
0 = REVP is updated on CF1
1 = REVP is updated on CF2
5
REVP_PULSE
0
0 = REVP is high when reverse polarity is true, low when reverse polarity is false
1 = REVP outputs a 1 Hz pulse when reverse polarity is true and is low when reverse polarity is false
6
ZXLPF
0
0 = ZX LPF is enabled
1 = ZX LPF is disabled
7
SWRST
0
Setting this bit enables a software reset
Rev. B | Page 62 of 72
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