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参数资料
| 型号： | ADF4002BRUZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/20页 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQUENCY SYNTH 16-TSSOP |
| 设计资源： | Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003) |
| 标准包装： | 1,000 |
| 类型： | 时钟/频率合成器（RF），相位检测器 |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.7 V ~ 3.3 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-ADF4002EBZ1-ND - BOARD EVAL FOR ADF4002 |
Data Sheet
ADF4002
Rev. C | Page 9 of 20
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4002 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Figure 18 shows the full truth table. Figure 14 shows the
MUXOUT section in block diagram form.
DGND
DVDD
CONTROL
MUX
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUXOUT
06052-
024
Figure 14. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive phase detector (PD) cycles is less
than 15 ns. With LDP set to 1, five consecutive cycles of less
than 15 ns are required to set the lock detect. It stays set at high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle. For PFD frequencies greater than 10 MHz,
analog lock detect is more accurate because of the smaller pulse
widths.
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 k nominal.
When lock has been detected, this output is high with narrow,
low going pulses.
INPUT SHIFT REGISTER
The ADF4002 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 13-bit N counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, as shown in the timing diagram (see Figure 2). Table 6
provides the truth table for these bits. Figure 15 shows a
summary of how the latches are programmed.
Table 6. C2, C1 Truth Table
Control Bits
Data Latch
C2
C1
0
R Counter
0
1
N Counter
1
0
Function Latch
1
Initialization Latch
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