参数资料
型号: ADF4002BRUZ-RL7
厂商: Analog Devices Inc
文件页数: 3/20页
文件大小: 0K
描述: IC PLL FREQUENCY SYNTH 16-TSSOP
设计资源: Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
标准包装: 1,000
类型: 时钟/频率合成器(RF),相位检测器
PLL:
输入: CMOS,TTL
输出: 时钟
电路数: 1
比率 - 输入:输出: 2:1
差分 - 输入:输出: 是/无
频率 - 最大: 400MHz
除法器/乘法器: 是/无
电源电压: 2.7 V ~ 3.3 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 带卷 (TR)
配用: EVAL-ADF4002EBZ1-ND - BOARD EVAL FOR ADF4002
Data Sheet
ADF4002
Rev. C | Page 11 of 20
REFERENCE COUNTER LATCH MAP
LDP
0
1
ABP2
ABP1
0
2.9ns
0
1
NOT ALLOWED
1
0
6.0ns
1
2.9ns
R14
R13
R12
..........
R3
R2
R1
0
..........
0
1
0
..........
0
1
0
2
0
..........
0
1
3
0
..........
1
0
4
.
..........
.
..........
.
..........
.
1
..........
1
0
16380
1
..........
1
0
1
16381
1
..........
1
0
16382
1
..........
1
16383
X = DON’T CARE
DB20 DB19
DB18 DB17 DB16
DB15 DB14 DB13 DB12
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0)
C1 (0)
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
ABP1
ABP2
T1
T2
LDP
DB21
DB22
DB23
0
X
RESERVED
LOC
K
DE
T
E
CT
PR
EC
ISI
O
N
TEST
MODE BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
DIVIDE RATIO
ANTIBACKLASH PULSE WIDTH
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION.
OPERATION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION.
06052-
025
Figure 16. Reference Counter Latch Map
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