参数资料
型号: ADF4002BRUZ-RL
厂商: Analog Devices Inc
文件页数: 4/20页
文件大小: 0K
描述: IC PLL FREQUENCY SYNTH 16-TSSOP
设计资源: Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
标准包装: 2,500
类型: 时钟/频率合成器(RF),相位检测器
PLL:
输入: CMOS,TTL
输出: 时钟
电路数: 1
比率 - 输入:输出: 2:1
差分 - 输入:输出: 是/无
频率 - 最大: 400MHz
除法器/乘法器: 是/无
电源电压: 2.7 V ~ 3.3 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 带卷 (TR)
配用: EVAL-ADF4002EBZ1-ND - BOARD EVAL FOR ADF4002
ADF4002
Data Sheet
Rev. C | Page 12 of 20
N COUNTER LATCH MAP
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0)
C1 (1)
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
X
DB21
DB22
DB23
G1
0
1
0
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
1
X
N13
N12
N11
N3
N2
N1
0
..........
0
..........
0
1
0
..........
0
1
0
..........
0
1
3
.
..........
.
..........
.
..........
.
1
..........
1
0
8188
1
..........
1
0
1
8189
1
..........
1
0
8190
1
..........
1
8191
X = DON’T CARE
RESERVED
13-BIT N COUNTER
RESERVED
CONTROL
BITS
C
P
GA
IN
N COUNTER DIVIDE RATIO
NOT ALLOWED
1
2
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.
OPERATION
CP GAIN
CHARGE PUMP CURRENT
SETTING 1 IS PERMANENTLY USED.
CHARGE PUMP CURRENT
SETTING 2 IS PERMANENTLY USED.
CHARGE PUMP CURRENT
SETTING 1 IS USED.
CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.
06052-
016
Figure 17. N Counter Latch Map
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