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参数资料
| 型号： | ADF4113HVBCPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC CHARGE PUMP HV SYNTH 20-LFCSP |
| 标准包装： | 5,000 |
| 类型： | 时钟/频率合成器，RF |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 4GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 20-LFCSP-VQ |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-ADF4113HVEB1Z-ND - BOARD EVALUATION FOR ADF4113HV EVAL-ADF4113EBZ2-ND - BOARD EVAL FOR ADF4113 1750MHZ EVAL-ADF4113EBZ1-ND - BOARD EVAL FOR ADF4113 EVAL-ADF411XEBZ1-ND - BOARD EVAL FOR ADF411X NO CHIP |
ADF4113HV
Data Sheet
Rev. B | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
CP
CPGND
AGND
AVDD
RFINA
RFINB
RSET
REFIN
16
15
14
13
12
11
10
9
DVDD
MUXOUT
LE
CE
DGND
CLK
DATA
VP
ADF4113HV
TOP VIEW
(Not to Scale)
0
62
23
-00
3
Figure 3. TSSOP Pin Configuration
0
622
3-
00
4
AGND
RFINB
RFINA
DATA
LE
MUXOUT
CLK
CE
A
V
D
A
V
D
R
E
F
IN
D
G
N
D
G
N
D
V
P
R
S
E
T
C
P
D
V
D
V
D
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
14
13
12
1
3
4
15
11
CPGND
2
5
7
6
8
9
1
0
1
9
2
0
1
8
1
7
1
6
ADF4113HV
TOP VIEW
(Not to Scale)
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic
Description
1
19
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.56 V for the ADF4113HV. The relationship between
ICP and RSET is ICPmax = 3/RSET. Therefore, with RSET = 4.7 kΩ, ICPmax = 640 μA.
2
20
CP
Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter; in turn, this
drives the external VCO.
3
1
CPGND
Charge Pump Ground. CPGND is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
5
4
RFINB
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF.
6
5
RFINA
Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
7
6, 7
AVDD
Analog Power Supply. The power supply can range from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AVDD must be the same value
as DVDD.
8
REFIN
Reference Input. This pin is a CMOS input with a nominal threshold of VDD/2, and an equivalent
input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be
ac-coupled.
9
9, 10
DGND
Digital Ground.
10
11
CE
Chip Enable. A Logic low on this pin powers down the device and puts the charge pump output
into three-state mode. Taking the pin high powers up the device depending on the status of the
Power-Down Bit PD1.
11
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
12
13
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
13
14
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches; the latch is selected using the control bits.
14
15
MUXOUT
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the
scaled reference frequency to be externally accessed.
15
16, 17
DVDD
Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane (1μF, 1nF) should be placed as close as possible to this pin. For best performance, the 1 μF
capacitor should be placed within 2 mm of the pin. The placing of the 1nF capacitor is less critical
but should still be within 5 mm of the pin. DVDD must have the same value as AVDD.
16
18
VP
Charge Pump Power Supply. VP can range from 13.5 V to 16.5 V and should be decoupled
appropriately.
N/A
21
EPAD
Exposed Pad. The exposed pad must be connected to AGND.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADF4113HVBCPZ-RL7 | 功能描述:IC CHARGE PUMP HV SYNTH 20-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4113HVBRUZ | 功能描述:IC CHARGE PUMP HV SYNTH 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4113HVBRUZ-RL | 功能描述:IC CHARGE PUMP HV SYNTH 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4113HVBRUZ-RL7 | 功能描述:IC CHARGE PUMP HV SYNTH 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4113HVSD1Z | 制造商:Analog Devices 功能描述:- Rail/Tube |
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