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参数资料
| 型号： | ADF4113HVBCPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/20页 |
| 文件大小： | 0K |
| 描述： | IC CHARGE PUMP HV SYNTH 20-LFCSP |
| 标准包装： | 5,000 |
| 类型： | 时钟/频率合成器，RF |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 4GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 20-LFCSP-VQ |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-ADF4113HVEB1Z-ND - BOARD EVALUATION FOR ADF4113HV EVAL-ADF4113EBZ2-ND - BOARD EVAL FOR ADF4113 1750MHZ EVAL-ADF4113EBZ1-ND - BOARD EVAL FOR ADF4113 EVAL-ADF411XEBZ1-ND - BOARD EVAL FOR ADF411X NO CHIP |
ADF4113HV
Data Sheet
Rev. B | Page 10 of 20
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 17 is a simplified schematic.
The PFD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that
there is no dead zone in the PFD transfer function and mini-
mizes phase noise and reference spurs. Two bits in the reference
counter latch, ABP2 and ABP1, control the width of the pulse.
See Figure 20. The only recommended setting for the antiback-
lash pulse width is 7.2 ns.
PROGRAMMABLE
DELAY
U3
CLR2
Q2
D2
U2
CLR1
Q1
D1
CHARGE
PUMP
DOWN
UP
HIGH
U1
ABP1
ABP2
R DIVIDER
N DIVIDER
CP OUTPUT
R DIVIDER
N DIVIDER
CP
CPGND
VP
06223-
017
Figure 17. PFD Simplified Schematic and Timing (in Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4113HV allows the user to
access various internal points on the chip. The state of MUXOUT
is controlled by M3, M2, and M1 in the function latch. Figure 22
shows the full truth table (function latch map). Figure 18 shows
the MUXOUT section in block diagram form.
CONTROL
MUX
DVDD
MUXOUT
DGND
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
06223-
018
Figure 18. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the AB counter
latch is set to 0, digital lock detect is set high when the phase
error on five consecutive phase detector (PD) cycles is less than
10 ns. With LDP set to 1, five consecutive cycles of less than
3 ns are required to set the lock detect. It stays high until a phase
error greater than 25 ns is detected on any subsequent PD cycle.
Operate the N-channel, open-drain, analog lock detect with a
10 k nominal external pull-up resistor. When lock has been
detected, this output is high with narrow low-going pulses.
INPUT SHIFT REGISTER
The ADF4113HV digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter comprising
a 6-bit A counter and a 13-bit B counter. Data is clocked into
the 24-bit shift register on each rising edge of CLK, MSB first.
Data is transferred from the shift register to one of three latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2, C1) in the shift register.
These are the two LSBs, DB1 and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 6. Figure 19
shows a summary of how the latches are programmed.
Table 6. C2, C1 Truth Table
Control Bits
C2
C1
Data Latch
0
R counter
0
1
N counter (A and B)
1
0
Function latch (including prescaler)
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| ADF4113HVBCPZ-RL7 | 功能描述:IC CHARGE PUMP HV SYNTH 20-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4113HVBRUZ | 功能描述:IC CHARGE PUMP HV SYNTH 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4113HVBRUZ-RL | 功能描述:IC CHARGE PUMP HV SYNTH 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4113HVBRUZ-RL7 | 功能描述:IC CHARGE PUMP HV SYNTH 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4113HVSD1Z | 制造商:Analog Devices 功能描述:- Rail/Tube |
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