参数资料
| 型号： | ADF4116BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | IC SYNTH PLL RF 550MHZ 16-TSSOP |
| 标准包装： | 96 |
| 类型： | 时钟/频率合成器，RF |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 550MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 551 (CN2011-ZH PDF) |
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ADF4116/ADF4117/ADF4118
Rev. D | Page 21 of 28
APPLICATIONS INFORMATION
LOCAL OSCILLATOR FOR THE
GSM BASE STATION TRANSMITTER
Figure 35 shows the ADF4117/ADF4118 being used with a
VCO to produce the LO for a GSM base station transmitter.
The reference input signal is applied to the circuit at FREFIN and,
in this case, is terminated in 50 Ω. A typical GSM system has a
13 MHz TCXO driving the reference input without a 50 Ω
termination. To have a channel spacing of 200 kHz (the GSM
standard), the reference input must be divided by 65, using the
on-chip reference divider of the ADF4117/ADF1118.
The charge pump output of the ADF4117/ADF1118 (Pin 2)
drives the loop filter. In calculating the loop filter component
values, a number of items need to be considered. In this example,
the loop filter was designed so that the overall phase margin for
the system is 45°. Other PLL system specifications include:
KD = 1 mA
KV = 12 MHz/V
Loop bandwidth = 20 kHz
FREF = 200 kHz
N = 4500
Extra reference spur attenuation = 10 dB
All of these specifications are needed and are used to produce
the loop filter component values shown in Figure 36.
The loop filter output drives the VCO, which, in turn, is fed back
to the RF input of the PLL synthesizer; it also drives the RF
output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output, and the
RFIN terminal of the synthesizer.
In a PLL system, it is important to know when the system is in
locked mode. In Figure 35, this is accomplished by using the
MUXOUT signal from the synthesizer. The MUXOUT pin can
be programmed to monitor various internal signals in the
synthesizer. One of these is the LD or lock-detect signal.
SHUTDOWN CIRCUIT
The attached circuit in Figure 36 shows how to shut down both
the ADF411x family and the accompanying VCO. The ADG702
switch goes open-circuit when a Logic 1 is applied to the IN
input. The low cost switch is available in both SOT-23 and
MSOP packages.
DIRECT CONVERSION MODULATOR
In some applications, a direct conversion architecture can be
used in base station transmitters. Figure 37 shows the
combination available from Analog Devices, Inc. to implement
this solution.
The circuit diagram shows the AD9761 being used with the
AD8346. The use of dual integrated DACs, such as the AD9761
with specified ±0.02 dB and ±0.004 dB gain and offset matching
characteristics, ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The local oscillator is implemented by using the ADF4117/
ADF4118. In this case, the FOX801BH-130 provides the stable
13 MHz reference frequency. The system is designed for
200 kHz channel spacing and an output center frequency of
1960 MHz. The target application is a WCDMA base station
transmitter. Typical phase noise performance from this LO is
85 dBc/Hz at a 1 kHz offset. The LO port of the AD8346 is
driven in single-ended fashion. LOIN is ac-coupled to ground
with the 100 pF capacitor, and LOIP is driven through the ac-
coupling capacitor from a 50 Ω source. An LO drive level between
6 dBm and 12 dBm is required. The circuit in Figure 37 gives a
typical level of 8 dBm.
The RF output is designed to drive a 50 Ω load, but it must be
ac-coupled as shown in Figure 37. If the I and Q inputs are
driven in quadrature by 2 V p-p signals, the resulting output
power is approximately 10 dBm.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADF4116BRUZ | 制造商:Analog Devices 功能描述:PLL, FREQUENCY SYNTHESIZER, 550MHZ, TSSO |
| ADF4116BRUZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4116BRUZ-REEL | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4116BRUZ-REEL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4116BRUZ-REEL7 | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
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