参数资料
| 型号： | ADF4116BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC SYNTH PLL RF 550MHZ 16-TSSOP |
| 标准包装： | 96 |
| 类型： | 时钟/频率合成器，RF |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 550MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 551 (CN2011-ZH PDF) |
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ADF4116/ADF4117/ADF4118
Rev. D | Page 24 of 28
INTERFACING
The ADF411x family has a simple SPI-compatible serial inter-
face for writing to the device. CLK, DATA, and LE control the
data transfer. When LE (latch enable) goes high, the 24 bits that
are clocked into the input register on each rising edge of CLK
are transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz
or one update every 1.2 μs. This is more than adequate for
systems that have typical lock times in hundreds of microseconds.
ADuC812 Interface
Figure 38 shows the interface between the ADF411x family and
the ADuC812 MicroConverter. Since the ADuC812 is based
on an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF411x family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the MicroConverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.
SCLOCK
MOSI
I/O PORTS
ADuC812
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4116/
ADF4117/
ADF4118
0
039
2-
0
38
Figure 38. ADuC812 to ADF411x family Interface
On first applying power to the ADF411x family, it requires three
writes (one each to the R counter latch, the N counter latch, and
the initialization latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed is 166 kHz.
ADSP-21xx Interface
Figure 39 shows the interface between the ADF411x family and
the ADSP-21xx digital signal processor. The ADF411x family
needs a 21-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated.
SCLK
DT
I/O FLAGS
ADSP-21xx
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4116/
ADF4117/
ADF4118
TFS
00
39
2-
03
9
Figure 39. ADSP-21xx to ADF411x family Interface
Set up the word length for 8 bits and use three memory
locations for each 24-bit word. To program each 21-bit latch,
store the three 8-bit bytes, enable the autobuffered mode, and
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADF4116BRUZ | 制造商:Analog Devices 功能描述:PLL, FREQUENCY SYNTHESIZER, 550MHZ, TSSO |
| ADF4116BRUZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4116BRUZ-REEL | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4116BRUZ-REEL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4116BRUZ-REEL7 | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
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