参数资料
| 型号： | ADF4117BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/28页 |
| 文件大小： | 0K |
| 描述： | IC PLL RF FREQ SYNTHESZR 16TSSOP |
| 标准包装： | 96 |
| 类型： | 时钟/频率合成器，RF |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
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ADF4116/ADF4117/ADF4118
Rev. D | Page 12 of 28
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 25. SW1 and SW2
are normally closed switches; SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
TO R COUNTER
REFIN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
BUFFER
00
39
2-
02
5
Figure 25. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 26. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
AVDD
AGND
500
1.6V
BIAS
GENERATOR
RFINA
RFINB
00
39
2-
0
26
Figure 26. RF Input Stage
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A counter
and B counter, enables the large division ratio, N, to be realized
(N = PB + A). The dual-modulus prescaler takes the CML clock
from the RF input stage and divides it down to a manageable
frequency for the CMOS A counter and CMOS B counter. The
prescaler is programmable. It can be set in software to 8/9 for the
ADF4116 and to 32/33 for the ADF4117 and ADF4118. It is based
on a synchronous 4/5 core.
A COUNTER AND B COUNTER
The A CMOS counter and B CMOS counter combine with the
dual-modulus prescaler to allow a wide ranging division ratio in
the PLL feedback counter. The counters are specified to work
when the prescaler output is 200 MHz or less.
Pulse Swallow Function
The A counter and B counter, in conjunction with the dual-
modulus prescaler, make it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The equation for the VCO frequency is as follows:
(
)
[
]
R
f
A
B
P
f
REFIN
VCO
/
×
+
×
=
where:
fVCO is the output frequency of external voltage controlled
oscillator (VCO).
P is the preset modulus of dual-modulus prescaler.
B is the preset divide ratio of binary 13-bit counter (3 to 8191).
A is the preset divide ratio of binary 5-bit swallow counter (0 to 31).
fREFIN is the output frequency of the external reference frequency
oscillator.
R is the preset divide ratio of binary 14-bit programmable
reference counter (1 to 16,383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the input clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
13-BIT
B COUNTER
5-BIT
A COUNTER
PRESCALER
P/P + 1
FROM RF
INPUT STAGE
MODULUS
CONTROL
N = BP + A
LOAD
TO PFD
0
039
2-
0
27
Figure 27. A Counter and B Counter
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADF4117BRUZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4117BRUZ-RL | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4117BRUZ-RL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4117BRUZ-RL7 | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4117BRUZ-RL71 | 制造商:AD 制造商全称:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
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