参数资料
| 型号： | ADF4151BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 32LFCSP |
| 标准包装： | 1 |
| 类型： | * |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 3.5GHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 托盘 |
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ADF4151
Data Sheet
Rev. B | Page 20 of 28
RF SYNTHESIZER—A WORKED EXAMPLE
The following is an example of how to program the ADF4151
synthesizer:
RFOUT = [INT + (FRAC/MOD)] × [fPFD]/RF Divider
(3)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
RF Divider is the output divider that divides down the VCO
frequency.
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(4)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
R is the RF reference division factor.
T is the reference divide-by-2 bit (0 or 1).
For example, in a UMTS system, where 2112.6 MHz RF
frequency output (RFOUT) is required, a 10 MHz reference
frequency input (REFIN) is available, and a 200 kHz channel
resolution (fRESOUT) is required on the RF output. A 2.1 GHz
VCO is suitable to cover the required fractional frequency of
2112.6 MHz.
fPFD
PFD
VCO
N
DIVIDER
RFOUT
10265-
025
Figure 25. Loop Closed Before Output Divider
A channel resolution (
fRES) of 200 kHz is required at the output
of the VCO.
MOD = REFIN/fRES
MOD = 10 MHz/200 kHz = 50
From Equation 4
fPFD = [10 MHz × (1 + 0)/1] = 10 MHz
(5)
2112.6 MHz = 10 MHz × (INT + FRAC/50)
(6)
where:
INT = 211
FRAC = 13
MODULUS
The choice of modulus (MOD) depends on the reference signal
(REFIN) available and the channel resolution (fRES) required at
the RF output. For example, a GSM system with 13 MHz REFIN
sets the modulus to 65. This means that the RF output resolution
(fRES) is the 200 kHz (13 MHz/65) necessary for GSM. With dither
off, the fractional spur interval depends on the modulus values
chosen (see Table 7).
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually improves noise performance by 3 dB. It is important
to note that the PFD cannot operate above maximum value (see
Table 1) due to a limitation in the speed of the Σ-Δ circuit of the
N-divider.
The reference divide-by-2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency. This is necessary
for the correct operation of the cycle slip reduction (CSR)
function. See the Cycle Slip Reduction for Faster Lock Times
section for more information.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4151 allows the
user to program the modulus over a 12-bit range. This means
that the user can set up the part in many different configurations
for the application, when combined with the reference doubler
and the 10-bit R counter.
For example, consider an application that requires 1.75 GHz RF
and 200 kHz channel step resolution. The system has a 13 MHz
reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. The 26 MHz is then fed
into the PFD, programming the modulus to divide by 130. This
also results in 200 kHz resolution and offers superior phase
noise performance over the previous setup.
The programmable modulus is also very useful for multi-
standard applications. If a dual-mode phone requires PDC
and GSM 1800 standards, the programmable modulus is a
great benefit. PDC requires 25 kHz channel step resolution,
whereas GSM 1800 requires 200 kHz channel step resolution.
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