参数资料
型号: ADF4151BCPZ
厂商: Analog Devices Inc
文件页数: 18/28页
文件大小: 0K
描述: IC PLL FREQ SYNTHESIZER 32LFCSP
标准包装: 1
类型: *
PLL:
输入: CMOS,TTL
输出: 时钟
电路数: 1
比率 - 输入:输出: 2:1
差分 - 输入:输出: 是/无
频率 - 最大: 3.5GHz
除法器/乘法器: 是/是
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘,CSP
供应商设备封装: 32-LFCSP-WQ(5x5)
包装: 托盘
Data Sheet
ADF4151
Rev. B | Page 25 of 28
INTERFACING
The ADF4151 has a simple SPI-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 32 bits that have been clocked
into the appropriate register on each rising edge of CLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 5 for the register address table.
ADuC812 Interface
Figure 30 shows the interface between the ADF4151 and the
ADuC812 MicroConverter. Because the ADuC812 is based
on an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4151 needs a
32-bit word, which is accomplished by writing four 8-bit bytes
from the MicroConverter to the device. When the fourth byte
has been written, the LE input should be brought high to
complete the transfer.
ADuC812
ADF4151
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLOCK
MOSI
I/O PORTS
10265-
030
Figure 30. ADuC812 to ADF4151 Interface
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and detect lock (MUXOUT configured as
lock detect and polled by the port input). When operating in
the described mode, the maximum SCLOCK rate of the
ADuC812 is 4 MHz. This means that the maximum rate at
which the output frequency can be changed is 125 kHz.
Blackfin BF527 Interface
Figure 31 shows the interface between the ADF4151 and the
Blackfin ADSP-BF527 digital signal processor (DSP). The
ADF4151 needs a 32-bit serial word for each latch write. The
easiest way to accomplish this using the Blackfin family is to use
the autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for eight bits and use four memory locations for each
32-bit word. To program each 32-bit latch, store the four 8-bit
bytes, enable the autobuffered mode, and write to the transmit
register of the DSP. This last operation initiates the autobuffer
transfer. As in the microcontroller case, just make sure that the
clock speeds are within the maximum limits outlined in Table 2.
ADSP-BF527
ADF4151
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLK
MOSI
GPIO
I/O FLAGS
10265-
031
Figure 31. ADSP-BF527 to ADF4151 Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-32-7) are rectangular.
The PCB pad for these must be 0.1 mm longer than the package
land length and 0.05 mm wider than the package land width.
The land is to be centered on the pad. This ensures that the
solder joint size is maximized. The bottom of the chip scale
package has a central thermal pad.
The thermal pad on the PCB must be at least as large as the
exposed pad. On the PCB, there is to be a minimum clearance
of 0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, they
are to be incorporated in the thermal pad at 1.2 mm pitch grid.
The via diameter must be between 0.3 mm and 0.33 mm, and
the via barrel must be plated with one ounce copper to plug
the via.
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