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| 型号： | ADF4154BRUZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/24页 |
| 文件大小： | 0K |
| 描述： | IC FRACTION-N FREQ SYNTH 16TSSOP |
| 标准包装： | 2,500 |
| 类型： | 分数 N 合成器（RF） |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 4GHz |
| 除法器/乘法器： | 无/是 |
| 电源电压： | 2.7 V ~ 3.3 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-ADF4154EBZ1-ND - BOARD EVALUATION FOR ADF4154EB1 |
ADF4154
Data Sheet
Rev. C | Page 6 of 24
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
ADF4154
TOP VIEW
(Not to Scale)
AGND
4
RFINB 5
RFINA 6
AVDD 7
REFIN 8
LE
DATA
CLK
SDVDD
DGND
13
12
11
10
RSET 1
CP 2
CPGND
3
VP
DVDD
MUXOUT
16
15
14
9
04
83
3
-00
2
Figure 3. TSSOP Pin Configuration
048
33-
003
14
13
12
1
3
4
LE
15 MUXOUT
DATA
CLK
11 SDVDD
CPGND
AGND
2
AGND
RFINB
5
RFINA
7
A
V
D
6
A
V
D
8
R
E
F
IN
9
D
G
N
D
1
0
D
G
N
D
1
9
R
S
E
T
2
0
C
P
1
8
V
P
1
7
D
V
D
1
6
D
V
D
ADF4154
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP
LFCSP
Mnemonic
Description
1
19
RSET
Set Resistor. Connecting a resistor between this pin and ground sets the maximum charge pump
output current. The relationship between ICP and RSET is
SET
CPmax
R
I
5
.
25
where RSET = 5.1 kΩ and ICPmax = 5 mA.
2
20
CP
Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn
drives the external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
5
4
RFINB
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF (see Figure 15).
6
5
RFINA
Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7
6, 7
AVDD
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be placed
as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same voltage as DVDD.
8
REFIN
Reference Input. This CMOS input has a nominal threshold of VDD/2 and an equivalent input resistance of
100 kΩ (see Figure 14). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9
9, 10
DGND
Digital Ground.
10
11
SDVDD
Σ- Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to
this pin. SDVDD has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD.
11
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
12
13
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a
high impedance CMOS input.
13
14
LE
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the
four latches, which is selected by the user via the control bits.
14
15
MUXOUT
Multiplexer Output. This pin allows either the RF lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
15
16, 17
DVDD
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same
voltage as AVDD.
16
18
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
N/A
EP
EPAD
Exposed Pad. The exposed pad must be connected to AGND.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADF4154BRUZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4155BCPZ | 功能描述:IC PLL FRAC-N FREQ SYNTH 20LFCSP 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:有效 类型:* PLL:是 输入:LVDS，LVPECL 输出:时钟 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/无 频率 - 最大值:4GHz 分频器/倍频器:是/无 电压 - 电源:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:24-WFQFN 裸露焊盘，CSP 供应商器件封装:24-LFCSP-WQ（4x4） 标准包装:1 |
| ADF4155BCPZ-RL7 | 功能描述:IC PLL FRAC-N FREQ SYNTH 20LFCSP 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:有效 类型:* PLL:是 输入:LVDS，LVPECL 输出:时钟 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/无 频率 - 最大值:4GHz 分频器/倍频器:是/是 电压 - 电源:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:24-WFQFN 裸露焊盘，CSP 供应商器件封装:24-LFCSP-WQ（4x4） 标准包装:1,500 |
| ADF4156 | 制造商:AD 制造商全称:Analog Devices 功能描述:6 GHz Fractional-N Frequency Synthesizer |
| ADF4156BCPZ | 功能描述:IC PLL FRAC-N FREQ SYNTH 20LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
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