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| 型号： | ADF4156BRUZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC PLL FRAC-N FREQ SYNTH 16TSSOP |
| 产品变化通告： | Improve Phase Noise Performance |
| 设计资源： | Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174) |
| 标准包装： | 2,500 |
| 类型： | 分数 N 合成器（RF） |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 6.2GHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 2.7 V ~ 3.3 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
Data Sheet
ADF4156
Rev. E | Page 3 of 24
SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 , unless otherwise noted.
Table 1.
Parameter
B Version
Unit
Test Conditions/Comments1
RF CHARACTERISTICS
RF Input Frequency (RFIN)
0.5/6.2
GHz min/max
10 dBm min to 0 dBm max. For lower frequencies,
ensure slew rate (SR) > 400 V/s.
REFERENCE CHARACTERISTICS
REFIN Input Frequency
10/250
MHz min/max
For f < 10 MHz, use a dc-coupled CMOS-compatible
square wave, slew rate > 25 V/s.
REFIN Input Sensitivity
0.4/AVDD
V p-p min/max
REFIN Input Capacitance
10
pF max
REFIN Input Current
±100
A max
PHASE DETECTOR
Phase Detector Frequency3
32
MHz max
CHARGE PUMP
ICP Sink/Source
Programmable.
High Value
5
mA typ
With RSET = 5.1 kΩ.
Low Value
312.5
A typ
Absolute Accuracy
2.5
% typ
With RSET = 5.1 kΩ.
RSET Range
2.7/10
kΩ min/max
ICP Three-State Leakage Current
1
nA typ
Sink and source current.
Matching
2
% typ
0.5 V < VCP < VP 0.5.
ICP vs. VCP
2
% typ
0.5 V < VCP < VP 0.5.
ICP vs. Temperature
2
% typ
VCP = VP/2.
LOGIC INPUTS
VINH, Input High Voltage
1.4
V min
VINL, Input Low Voltage
0.6
V max
IINH/IINL, Input Current
±1
A max
CIN, Input Capacitance
10
pF max
LOGIC OUTPUTS
VOH, Output High Voltage
1.4
V min
Open-drain output chosen; 1 kΩ pull-up to 1.8 V.
VOH, Output High Voltage
VDD 0.4
V min
CMOS output chosen.
IOH, Output High Current
100
A max
VOL, Output Low Voltage
0.4
V max
IOL = 500 A.
POWER SUPPLIES
AVDD
2.7/3.3
V min/max
DVDD
AVDD
VP
AVDD/5.5
V min/max
IDD
32
mA max
26 mA typical.
Low Power Sleep Mode
1
A typ
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PNSYNTH)4
220
dBc/Hz typ
PLL loop BW = 500 kHz. Measured at 100 kHz offset.
Normalized 1/f Noise (PN1_f)5
110
dBc/Hz typ
10 kHz offset; normalized to 1 GHz.
Phase Noise Performance6
At VCO output.
5800 MHz Output7
89
dBc/Hz typ
At 5 kHz offset, 25 MHz PFD frequency.
1
Operating temperature for B version: 40°C to +85°C.
2
AC coupling ensures AVDD/2 bias.
3
Guaranteed by design. Sample tested to ensure compliance.
4
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(FPFD). PNSYNTH = PNTOT 10 log(FPFD) 20 log(N).
5
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,
and at a frequency offset f is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6
The phase noise is measured with the EV-ADF4156SD1Z evaluation board and the Agilent E5500 phase noise system.
7
fREFIN = 100 MHz, fPFD = 25 MHz, offset frequency = 5 kHz, RFOUT = 5800 MHz, N = 232, loop bandwidth = 20 kHz, ICP = 313 A, and lowest noise mode.
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| ADF4156BRUZ-RL7 | 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4156SP1BRUZ | 制造商:Analog Devices 功能描述: |
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| ADF4157BCPZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer |
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