参数资料
型号: ADF4216BRU-REEL
厂商: Analog Devices Inc
文件页数: 1/20页
文件大小: 0K
描述: IC PLL FREQ SYNTHESIZER 20-TSSOP
产品变化通告: ADF4213,16 Discontinuation 15/May/2012
标准包装: 2,500
类型: 时钟/频率合成器(RF/IF)
PLL:
输入: CMOS,TTL
输出: 时钟
电路数: 1
比率 - 输入:输出: 3:1
差分 - 输入:输出: 是/无
频率 - 最大: 1.2GHz
除法器/乘法器: 是/无
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 带卷 (TR)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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ADF4216/ADF4217/ADF4218
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
Dual RF PLL Frequency Synthesizers
FUNCTIONAL BLOCK DIAGRAM
22-BIT
DATA
REGISTER
SDOUT
OSCILLATOR
CLOCK
DATA
LE
IF
LOCK
DETECT
MUXOUT
ADF4216/ADF4217/ADF4218
CP
RF
CP
IF
CHARGE
PUMP
PHASE
COMPARATOR
OUTPUT
MUX
REF
IN
RF
PRESCALER
RFINA
CHARGE
PUMP
PHASE
COMPARATOR
RF
LOCK
DETECT
V
DD1VDD2VP1VP2
AGND
RF
DGND
RF
DGND
IF
AGND
IF
RFINB
DGND
IF
PRESCALER
IFINA
11-BIT IF
B-COUNTER
6-BIT IF
A-COUNTER
IFINB
N = BP + A
14-BIT IF
R-COUNTER
14-BIT IF
R-COUNTER
11-BIT RF
B-COUNTER
6-BIT RF
A-COUNTER
FEATURES
ADF4216: 550 MHz/1.2 GHz
ADF4217: 550 MHz/2.0 GHz
ADF4218: 550 MHz/2.5 GHz
2.7 V to 5.5 V Power Supply
Selectable Charge Pump Currents
Selectable Dual Modulus Prescaler
IF: 8/9 or 16/17
RF: 32/33 or 64/65
3-Wire Serial Interface
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
GENERAL DESCRIPTION
The ADF4216/ADF4217/ADF4218 are dual frequency synthe-
sizers that can be used to implement local oscillators (LOs) in
the upconversion and downconversion sections of wireless
receivers and transmitters. They can provide the LO for both
the RF and IF sections. They consist of a low-noise digital PFD
(Phase Frequency Detector), a precision charge pump, a pro-
grammable reference divider, programmable A and B counters,
and a dual-modulus prescaler (P/P+1). The A (6-bit) and B
(11-bit) counters, in conjunction with the dual modulus prescaler
(P/P+1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R Counter), allows selectable
REFIN frequencies at the PFD input. A complete PLL (Phase-
Locked Loop) can be implemented if the synthesizers are
used with an external loop lter and VCOs (Voltage Con-
trolled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V
to 5.5 V and can be powered down when not in use.
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