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参数资料
| 型号： | ADF4252BCPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 24LFCSP |
| 标准包装： | 1,500 |
| 类型： | 时钟/频率合成器（RF/IF），分数-N，整数-N， |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:2 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.7 V ~ 3.3 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 24-LFCSP-VQ（4x4） |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-ADF4252EBZ2-ND - BOARD EVAL ADF4252 NO VCO/FILTER |
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REV. B
ADF4252
–21–
RF N DIVIDER REGISTER
(Address R0)
With R0[2, 1, 0] set to [0, 0, 0], the on-chip RF N divider register
will be programmed. Table III shows the input data format for
programming this register.
8-Bit RF INT Value
These eight bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor. It is used in
Equation 1.
12-Bit RF FRAC Value
These 12 bits control what is loaded as the FRAC value into the
fractional interpolator. This is part of what determines the overall
feedback division factor. It is used in Equation 1. The FRAC
value must be less than or equal to the value loaded into the
MOD register.
RF R DIVIDER REGISTER
(Address R1)
With R1[2, 1, 0] set to [0, 0, 1], the on-chip RF R divider register
will be programmed. Table IV shows the input data format for
programming this register.
RF Prescaler (P/P + 1)
The RF dual-modulus prescaler (P/P +1), along with the INT,
FRAC, and MOD counters, determine the overall division ratio
from the RFIN to the PFD input. Operating at CML levels, it
takes the clock from the RF input stage and divides it down to
amanageable frequency for the CMOS counters. It is based on
a synchronous 4/5 core (see Table IV).
RF REFIN Doubler
Setting this bit to 0 feeds the REFIN signal directly to the 4-bit
RF R counter, disabling the doubler. Setting this bit to 1 multiplies
the REFIN frequency by a factor of 2 before feeding into the
4-bit RF R counter. When the doubler is disabled, the REFIN
falling edge is the active edge at the PFD input to the fractional-N
synthesizer. When the doubler is enabled, both the rising and
falling edges of REFIN become active edges at the PFD input.
When the doubler is enabled and lowest spur mode is chosen,
the in-band phase noise performance is sensitive to the REFIN
duty cycle. The phase noise degradation can be as much as 5 dB
for REFIN duty cycles outside a 45% to 55% range. The phase
noise is insensitive to REFIN duty cycle in the lowest noise mode
and in low noise and spur mode. The phase noise is insensitive
to REFIN duty cycle when the doubler is disabled.
4-Bit RF R Counter
The 4-bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the phase frequency detector (PFD). Division ratios from 1 to
15 are allowed.
12-Bit Interpolator Modulus
This programmable register sets the fractional modulus. This is
the ratio of the PFD frequency to the channel step resolution on
the RF output.
RF CONTROL REGISTER
(Address R2)
With R2[2, 1, 0] set to [0, 1, 0], the on-chip RF control register
will be programmed. Table V shows the input data format for
programming this register. Upon initialization, DB15–DB11
should all be set to 0.
Noise and Spur Setting
The noise and spur setting (R2[15, 11, 06]) is a feature that
allows the user to optimize his or her design either for improved
spurious performance or for improved phase noise performance.
When set to [0, 0, 0], the lowest spurs setting is chosen. Here,
dither is enabled. This randomizes the fractional quantization
noise so that it looks more like white noise than spurious noise.
This means that the part is optimized for improved spurious
performance. This operation would normally be used when the
PLL closed-loop bandwidth is wide
1, for fastlocking applications.
A wide-loop filter does not attenuate the spurs to a level that a
narrow-loop
2 bandwidth would. When this bit is set to [0, 0, 1],
the low noise and spur setting is enabled. Here, dither is disabled.
This optimizes the synthesizer to operate with improved noise
performance. However, the spurious performance is degraded in
this mode compared to lowest spurs setting. To improve noise
performance even further, another option is available that reduces
the phase noise. This is the lowest noise setting [1, 1, 1]. As well
as disabling the dither, it also ensures the charge pump is oper-
ating in an optimum region for noise performance. This setting is
extremely useful where a narrow-loop filter bandwidth is available.
The synthesizer ensures extremely low noise and the filter attenu-
ates the spurs. The Typical Performance Characteristics (TPCs)
give the user an idea of the trade-off in a typical WCDMA setup
for the different noise and spur settings.
RF Counter Reset
DB3 is the RF counter reset bit for the ADF4252. When this is
1, the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
RF Charge Pump Three-State
This bit puts the charge pump into three-state mode when pro-
grammed to a 1. It should be set to 0 for normal operation.
RF Power-Down
DB5 on the ADF4252 provides the programmable power-down
mode. Setting this bit to a 1 will perform a power-down on both
the RF and IF sections. Setting this bit to 0 will return the RF
and IF sections to normal operation. While in software
power-down, the part will retain all information in its registers.
Only when supplies are removed will the register contents be lost.
When a power-down is activated, the following events occur:
1. All active RF dc current paths are removed.
2. The RF synthesizer counters are forced to their load state
conditions.
3. The RF charge pump is forced into three-state mode.
4. The RF digital lock detect circuitry is reset.
5. The RFIN input is debiased.
6. The input register remains active and capable of loading and
latching data.
NOTES
1Wide-loop bandwidth is seen as a loop bandwidth greater than 1/10th of the
RFOUT channel step resolution (FRES).
2Narrow-loop bandwidth is seen as a loop bandwidth less than 1/10th of the
RFOUT channel step resolution (FRES).
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| ADF4252BCPZ-RL | 功能描述:IC PLL FREQ SYNTHESIZER 24LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4350 | 制造商:AD 制造商全称:Analog Devices 功能描述:Wideband Synthesizer with Integrated VCO |
| ADF4350ABCPZ | 制造商:Analog Devices 功能描述:F-N WITH HIGH PERFORMANCE INTEGRATED VCO - Trays |
| ADF4350ABCPZ-RL7 | 制造商:Analog Devices 功能描述:F-N WITH HIGH PERFORMANCE INTE 制造商:Analog Devices 功能描述:F-N WITH HIGH PERFORMANCE INTEGRATED VCO - Tape and Reel |
| ADF4350BCPZ | 功能描述:IC SYNTH PLL VCO FN/IN 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
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