参数资料
| 型号： | ADF4360-5BCPZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/24页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER VCO 24LFCSP |
| 标准包装： | 1,500 |
| 类型： | 扇出配送，整数-N，合成器（RF） |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 1.4GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 24-LFCSP-VQ（4x4） |
| 包装： | 带卷 (TR) |
ADF4360-5
Data Sheet
Rev. B | Page 10 of 24
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 13 shows
the MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any sub-
sequent PD cycle.
The N-channel open-drain analog lock detect should be operat-
ed with an external pull-up resistor of 10 k nominal. When a
lock has been detected, the output is high with narrow low-
going pulses.
R COUNTER OUTPUT
N COUNTER OUTPUT
DIGITAL LOCK DETECT
DGND
CONTROL
MUX
MUXOUT
DVDD
ANALOG LOCK DETECT
SDOUT
04439-013
Figure 13. MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF4360 family’s digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter,
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs are DB1 and
DB0, as shown in Figure 2.
a summary of how the latches are programmed. Note that the
test mode latch is used for factory testing and should not be
programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
C2
C1
Data Latch
0
Control Latch
0
1
R Counter
1
0
N Counter (A and B)
1
Test Mode Latch
VCO
The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 14, to allow a wide frequency range
to be covered without a large VCO sensitivity (KV) and resultant
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at pow-
er-up. This sequence is
1. R counter latch
2. Control latch
3. N counter latch
During band selection, which takes five PFD cycles, the VCO
VTUNE is disconnected from the output of the loop filter and is
connected to an internal reference voltage.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1000
1100
1200
1150
1050
1350
1300
1250
1400 1450 1500
FREQUENCY (MHz)
V
TUNE
(V)
04439-014
Figure 14. Frequency vs. VTUNE, ADF4360-5
The R counter output is used as the clock for the band select logic
and should not exceed 1 MHz. A programmable divider is provid-
ed at the R counter input to allow division by 1, 2, 4, or 8 and is
controlled by Bits BSC1 and BSC2 in the R counter latch. Where
the required PFD frequency exceeds 1 MHz, the divide ratio should
be set to allow enough time for correct band selection.
After band select, normal PLL action resumes. The nominal value
of KV is 31 MHz/V or 15 MHz/V if divide-by-2 operation has been
selected (by programming DIV2 [DB22] high in the N counter
latch). The ADF4360 family contains linearization circuitry to min-
imize any variation of the product of ICP and KV.
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相关代理商/技术参数 |
参数描述 |
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| ADF4360-6 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MHz to 6 GHz Broadband Quadrature Modulator |
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