参数资料
| 型号： | ADF4360-5BCPZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/24页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER VCO 24LFCSP |
| 标准包装： | 1,500 |
| 类型： | 扇出配送，整数-N，合成器（RF） |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 1.4GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 24-LFCSP-VQ（4x4） |
| 包装： | 带卷 (TR) |
ADF4360-5
Data Sheet
Rev. B | Page 16 of 24
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-5 after
power-up is:
1. R counter latch
2. Control latch
3. N counter latch
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AVDD, DVDD, VVCO, and CE pins. On
initial power-up, an interval is required between programming
the control latch and programming the N counter latch.
This interval is necessary to allow the transient behavior of the
ADF4360-5 during initial power-up to have settled. During
initial power-up, a write to the control latch powers up the part
and the bias currents of the VCO begins to settle. If these cur-
rents have not settled to within 10% of their steady-state value
and if the N counter latch is then programmed, the VCO may
not be able to oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency band
and the ADF4360-5 may not achieve lock. If the recommended
interval is inserted and the N counter latch is programmed, the
band select logic can choose the correct frequency band and the
part locks to the correct frequency.
The duration of this interval is affected by the value of the ca-
pacitor on the CN pin (Pin 14). This capacitor is used to reduce
the close-in noise of the ADF4360-5 VCO. The recommended
value of this capacitor is 10 F. Using this value requires an in-
terval of ≥ 5 ms between the latching in of the control latch bits
and latching in of the N counter latch bits. If a shorter delay is
required, this capacitor can be reduced. A slight phase noise
penalty is incurred by this change, which is explained further in
Table 10. CN Capacitance vs. Interval and Phase Noise
CN Value
Recommended Interval between Control Latch and N Counter Latch
Open-Loop Phase Noise @ 10 kHz Offset
10 F
≥ 5 ms
88 dBc
440 nF
≥ 600 s
87 dBc
CLOCK
POWER-UP
DATA
LE
R COUNTER
LATCH DATA
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
04439-020
Figure 16. ADF4360-5 Power-Up Timing
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADF4360-6 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MHz to 6 GHz Broadband Quadrature Modulator |
| ADF4360-6BCP | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:INT. SYNTHESIZER & VCO - 1000 - 1250 MHZ - Bulk 制造商:Analog Devices 功能描述:IC SYNTHESIZER PLL |
| ADF4360-6BCPRL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP T/R |
| ADF4360-6BCPRL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP T/R 制造商:Rochester Electronics LLC 功能描述:INT. SYNTHESIZER & VCO - 1000 - 1250 MHZ - Bulk |
| ADF4360-6BCPU1 | 制造商:Analog Devices 功能描述:FRAC-N PLL AND VCO - Bulk |
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