参数资料
型号: ADF7011BRUZ-REEL
厂商: ANALOG DEVICES INC
元件分类: 通信及网络
英文描述: SPECIALTY TELECOM CIRCUIT, PDSO24
封装: MO-153AD, TSSOP-24
文件页数: 11/24页
文件大小: 567K
代理商: ADF7011BRUZ-REEL
REV. 0
ADF7011
–19–
MODULATION SCHEMES
Frequency Shift Keying (FSK)
Frequency shift keying is implemented by setting the N value
for the center frequency and then toggling this with the TxDATA
line. The deviation from the center frequency is set using Bits
D1–D7 in the modulation register. The deviation from the
center frequency in Hz is
FSK
Hz
PFD Frequency
Modulation Number
DEVIATION
() =
×
2
12
The modulation number is a number from 1 to 127 (Bits D1–
D7 in modulation register). FSK is selected by setting Bits S1
and S2 to zero in the modulation register.
R
PFD/
CHARGE
PUMP
INTEGER-N
FRACTIONAL-N
THIRD ORDER
-
MODULATOR
–FDEV
+FDEV
TxDATA
FSK DEVIATION
FREQUENCY
INTERNAL VCO USING
SPIRAL INDUCTORS
GAIN 70 MHz/V–90 MHz/V
PA STAGE
CHEAP AT CRYSTAL
VCO
Figure 13. FSK Implementation
Gaussian Frequency Shift Keying (GFSK)
Gaussian frequency shift keying reduces the bandwidth occupied
by the transmitted spectrum by digitally prefiltering the TxDATA.
A TxCLK output line is provided from the ADF7011 for syn-
chronization of TxDATA from the microcontroller. The TxCLK
line may be connected to the clock input of an external shift
register that clocks data to the transmitter at exact data rate.
SHIFT
REGISTER
ADF7011
DATA FROM
MICROCONTROLLER
TxDATA
TxCLK
ANTENNA
Figure 14. TxCLK Pin Synchronizing Data for GFSK
Setting Up the ADF7011 for GFSK
To set up the frequency deviation, set the PFD and the mod
control Bits MC1 to MC3.
GFSK
Hz
PFD Frequency
DEVIATION
m
() =
× 2
2
12
where m is mod control (Bits MC1 to MC3 in the modulation
register).
To set up the GFSK data rate
Data Rate bits s
PFD Frequency
Divider Factor
Index Counter
/
() =
×
Amplitude Shift Keying (ASK)
Amplitude shift keying is implemented by switching the output
stage between two discrete power levels. This is implemented by
toggling the DAC, which controls the output level between two
7-bit values set up in the modulation register. A zero TxDATA
bit sends Bits D1–D7 to the DAC. A high TxDATA bit sends
Bits P1–P7 to the DAC. A maximum modulation depth of 30 dB
is possible. ASK is selected by setting Bit S2 = 1 and Bit S1 = 0.
On-Off Keying (OOK)
On-off keying is implemented by switching the output stage to a
certain power level for a high TxDATA bit and switching the
output stage off for a zero. Due to feedthrough effects, a maximum
modulation depth of 33 dB is specified. For OOK, the transmitted
power for a high input is programmed using Bits P1–P7 in the
modulation register. OOK is selected by setting Bits S1 and S2
to 1 in the modulation register.
CHOOSING CHANNELS FOR BEST SYSTEM
PERFORMANCE
The fractional-N PLL allows the selection of any channel within
868 MHz to 870 MHz to a resolution of <l00 Hz, as well as
facilitating frequency hopping systems.
Careful selection of the RF transmit channels must be made to
achieve best spurious performance. The architecture of frac-
tional-N results in some level of the nearest integer channel
moving through the loop to the RF output. These “beat-note”
spurs are not attenuated by the loop if the desired RF channel
and the nearest integer channel are separated by a frequency of
less than the loop BW.
The occurrence of beat-note spurs is rare, as the integer frequen-
cies are at multiples of the reference, which is typically >4 MHz.
The beat-note spurs can be significantly reduced in amplitude
by avoiding very small or very large values in the fractional
register. By having a channel 1 MHz away from an integer fre-
quency, a 100 kHz loop filter will reduce the level to < –45 dBc.
When using an external VCO, the Fast Lock (bleed) function will
reduce the spurs to < –60 dBc for the same conditions above.
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