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| 型号： | ADG1439BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/20页 |
| 文件大小： | 0K |
| 描述： | IC MULTIPLEXER DL 4X1 20TSSOP |
| 标准包装： | 75 |
| 系列： | iCMOS® |
| 功能： | 多路复用器 |
| 电路： | 2 x 4:1 |
| 导通状态电阻： | 21.5 欧姆 |
| 电压电源： | 单/双电源 |
| 电压 - 电源，单路/双路(±)： | 5 V ~ 16.5 V，±2.25 V ~ 8.25 V |
| 电流 - 电源： | 1nA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 802 (CN2011-ZH PDF) |
ADG1438/ADG1439
Rev. A | Page 12 of 20
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
10
VDD
DIN
GND
S2A
S1A
NC
SCLK
DA
S4A
S3A
20
19
18
17
16
15
14
13
12
11
VL
SDO
RESET
S2B
S1B
VSS
DB
S4B
S3B
SYNC
ADG1439
TOP VIEW
(Not to Scale)
08
496
-10
7
Figure 7. ADG1439 Pin Configuration (TSSOP)
PIN 1
INDICATOR
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD TIED TO SUBSTRATE, VSS.
1
DIN
2
GND
3
S1A
4
S2A
5
S3A
13 S1B
14 VSS
15 RESET
12 S2B
11 S3B
6
S
4
A
7
D
A
8
N
C
1
0
S
4
B
9
D
B
1
8
S
Y
N
C
1
9
S
C
L
K
2
0
V
D
1
7
V
L
1
6
S
D
O
TOP VIEW
(Not to Scale)
ADG1439
08
49
6-
10
8
Figure 8. ADG1439 Pin Configuration (LFCSP)
Table 11. ADG1439 Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Description
1
19
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates of up to 50 MHz.
2
20
VDD
Most Positive Power Supply Potential.
3
1
DIN
Serial Data Input. This device has an 8-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
4
2
GND
Ground (0 V) Reference.
5
8
NC
No Connect.
6
3
S1A
Source Terminal 1A. Can be an input or an output.
7
4
S2A
Source Terminal 2A. Can be an input or an output.
8
5
S3A
Source Terminal 3A. Can be an input or an output.
9
6
S4A
Source Terminal 4A. Can be an input or an output.
10
7
DA
Drain Terminal A. Can be an input or an output.
11
9
DB
Drain Terminal B. Can be an input or an output.
12
10
S4B
Source Terminal 4B. Can be an input or an output.
13
11
S3B
Source Terminal 3B. Can be an input or an output.
14
12
S2B
Source Terminal 2B. Can be an input or an output.
15
13
S1B
Source Terminal 1B. Can be an input or an output.
16
14
VSS
Most Negative Power Supply Potential. In single-supply applications, it can be connected
to ground.
17
15
RESET
Active Low Logic Input. When this pin is low, all switches are open, and appropriate registers are
cleared to 0.
18
16
SDO
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for
reading back the data in the shift register for diagnostic purposes. The serial data is transferred on
the rising edge of SCLK and is valid on the falling edge of the clock. This is an open-drain output
that should be pulled to the VL supply with an external 1 kΩ resistor.
19
17
VL
Logic Power Supply Input. Operates from 2.7 V to 5.5 V.
20
18
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is
transferred in on the falling edges of the following clocks. Taking SYNC high updates the switch
condition.
EPAD
The exposed pad is tied to the substrate, VSS.
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