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参数资料
| 型号： | ADG729BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/13页 |
| 文件大小： | 0K |
| 描述： | IC MUX/DEMUX DUAL 4X1 16TSSOP |
| 产品培训模块： | Switch Fundamentals |
| 标准包装： | 96 |
| 功能： | 多路复用器/多路分解器 |
| 电路： | 2 x 4:1 |
| 导通状态电阻： | 4.5 欧姆 |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 2.7 V ~ 5.5 V |
| 电流 - 电源： | 10µA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
–10–
ADG728/ADG729
WRITE OPERATION
When writing to the ADG728/ADG729, the user must begin
with an address byte and R/
W bit, after which the switch will
acknowledge that it is prepared to receive data by pulling SDA
low. This address byte is followed by the 8-bit word. The write
operations for each matrix switch are shown in the gures below.
SCL
SDA
S8
S7
S6
S5
S4
S3
S2
S1
00
1
A0
R/
W
STOP
COND
BY
MASTER
ACK
BY
ADG728
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
ACK
BY
ADG728
A1
1
Figure 16. ADG728 Write Sequence
SCL
SDA
S8
S7
S6
S5
S4
S3
S2
S1
00
1
A0
R/
W
STOP
COND
BY
MASTER
ACK
BY
ADG729
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
ACK
BY
ADG729
A1
1
0
Figure 17. ADG729 Write Sequence
READ OPERATION
When reading data back from the ADG728/ADG729, the user must begin with an address byte and R/
W bit, after which the ma-
trix switch will acknowledge that it is prepared to transmit data by pulling SDA low. The readback operation is a single byte that
consists of the eight data bits in the input register. The read operations for each part are shown in Figures 18 and 19.
SCL
SDA
S8
S7
S6
S5
S4
S3
S2
S1
00
1
A0
R/
W
STOP
COND
BY
MASTER
ACK
BY
ADG728
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
NO ACK
BY
MASTER
A1
1
Figure 18. ADG728 Readback Sequence
SCL
SDA
S8
S7
S6
S5
S4
S3
S2
S1
00
1
A0
R/
W
STOP
COND
BY
MASTER
ACK
BY
ADG729
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
NO ACK
BY
MASTER
A1
1
0
Figure 19. ADG729 Readback Sequence
REV. C
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