参数资料
型号: ADG739BRUZ-REEL7
厂商: Analog Devices Inc
文件页数: 18/20页
文件大小: 0K
描述: IC MUX/DEMUX DUAL 4X1 16TSSOP
产品培训模块: Switch Fundamentals
标准包装: 1,000
功能: 多路复用器/多路分解器
电路: 2 x 4:1
导通状态电阻: 4.5 欧姆
电压电源: 单电源
电压 - 电源,单路/双路(±): 2.7 V ~ 5.5 V
电流 - 电源: 10µA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 带卷 (TR)
其它名称: ADG739BRUZ-REEL7-ND
ADG739BRUZ-REEL7TR
Data Sheet
ADG738/ADG739
Rev. A | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADG738 Pin Configuration
Table 5. ADG738 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
These devices can accommodate serial input rates of up to 30 MHz.
2
RESET
Active Low Control Input. This pin clears the input register and turns all switches to the off condition.
3
DIN
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial clock input.
4, 5, 6, 7
S1, S2, S3, S4
Source. May be an input or output.
8
D
Drain. May be an input or output.
9, 10, 11, 12
S8, S7, S6, S5
Source. May be an input or output.
13
V
DD
Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
14
GND
Ground Reference.
15
DOUT
Data Output. This allows a number a parts to be daisy-chained. Data is clocked out of the input shift
register on the rising edge of SCLK. This is an open drain output, which should be pulled to the supply
with an external resistor.
16
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low,
it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on the
falling edges of the following clocks. Taking SYNC high updates the switch conditions.
SCLK
RESET
S2
S3
S4
S1
D
SYNC
DOUT
S5
S6
S7
GND
VDD
S8
DIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADG738
TOP VIEW
(Not to Scale)
10758-
004
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