参数资料
| 型号： | ADL5315-EVAL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADL5315 |
| 设计资源： | Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电流镜像 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADL5315 |
| 主要属性： | 电流镜像，高端，3nA ~ 3mA |
| 次要属性： | 2.7 ~ 8 V 1% 线性可调式输入电流限制 |
| 已供物品： | 板 |
| 相关产品： | ADL5315ACPZ-R7DKR-ND - IC CURRENT MONITOR 8LFCSP ADL5315ACPZ-R7CT-ND - IC CURRENT MONITOR 8LFCSP ADL5315ACPZ-R7TR-ND - IC CURRENT MONITOR 8LFCSP |
ADL5315
TRANSLINEAR LOG AMP INTERFACING
The mirror current output, IOUT, of the ADL5315 is designed
to interface directly to an Analog Devices translinear
logarithmic amplifier, such as the AD8304 , AD8305 , or
the ADL5315 to the AD8305. In this configuration, the designer
can use the full current mirror range of the ADL5315 for high
accuracy power monitoring.
The measured rms noise voltage at the output of the AD8305 vs.
the input current is shown in Figure 23, both for the AD8305 by
itself and in cascade with the ADL5315. The relatively low noise
produced by the ADL5315, combined with the additional noise
filtering inherent in the frequency response characteristics of
the AD8305, results in minimal degradation to the noise
Careful consideration should be made to the layout of the
circuit board in this configuration. Leakage current paths in the
board itself could lead to measurement errors at the output of
the translinear log amp, particularly when measuring the low
end of the ADL5315’s dynamic range. It is recommended that
when designing such an interface that a guard potential be used
to minimize this leakage. This can be done by connecting the
translinear log amp’s VSUM pin to the NC pin of the ADL5315,
with the VSUM guard trace running on both sides of the IOUT
trace. Additional details on using VSUM can be found in the
AD8304 or AD8305 data sheets. The VSET pin of the ADL5315
can be used in a similar fashion to guard the INPT trace.
5.5m
5.0m
4.5m
4.0m
performance of the AD8305.
3.5m
3.0m
2.5m
2.0m
1.5m
1.0m
0.5m
AD8305 AND
ADL5315
AD8305 ONLY
0
1n
10n
100n
1 μ
10 μ
100 μ
1m
I INPT (A)
Figure 23. Measured RMS Noise of AD8305 vs. AD8305
Cascaded with ADL5315
4
VOLTAGE
REFERENCE
ADL5315
CURRENT
LIMITING
5
V POS
R LIM = 48V – 3k Ω
I LIM
R LIM
COMM
20k Ω
CURRENT
RLIM
I LIM = 1mA – 16mA
16
15
14
13
MIRROR
3
1:1
6
C SET
SREF
VPOS
1
VRDZ
VOUT
12
2
1
VSET
INPT
I PD
I PD
NC
IOUT
7
8
1k Ω
200k Ω
4.7nF 2k Ω
2
3
4
VREF
IREF
INPT
AD8305
SCAL
BFIN
VLOG
11
10
9
OUTPUT
V OUT = 0.2 × LOG 10 (I PDM /1nA)
PIN
1nF
5
6
7
8
TIA
DATA PATH
AD8305 INPUT
COMPENSATION
0.1 μ F
3V TO 12V
NETWORK
Figure 24. Interfacing the ADL5315 to the AD8305 for High Accuracy PIN Power Monitoring
Rev. 0 | Page 12 of 20
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