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| 型号： | ADM1024EVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/30页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADM1024 |
| 标准包装： | 1 |
| 其它名称： | EVAL-ADM1024EB EVAL-ADM1024EB-ND |
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ADM1024
http://onsemi.com
20
operate as level-triggered interrupt inputs, with VID0/IRQ0
to VID2/IRQ2 being active low and VID3/IRQ3 and
VID4/IRQ4 being active high. The individual interrupt
inputs can be enabled or masked by setting or clearing Bits 4
to 6 of the Channel Mode Register and Bits 6 and 7 of
Configuration Register 2 (address 4Ah). These interrupt
inputs are not latched in the ADM1024, so they do not
require clearing as do bits in the Status Registers. However,
the external interrupt source should be cleared once the
interrupt has been services, or the interrupt request will be
reasserted.
Interrupt Clearing
Reading an Interrupt Status Register will output the
contents of the Register, then clear it. It will remain cleared
until the monitoring cycle updates it, so the next read
operation should not be performed on the register until this
has happened, or the result will be invalid. The time taken for
a complete monitoring cycle is mainly dependent on the
time taken to measure the fan speeds, as described earlier.
The INT output is cleared with the INT_Clear bit, which
is Bit 3 of the Configuration Register, without affecting the
contents of the Interrupt (INT) Status Registers.
Interrupt Status Mirror Registers
Whenever a bit in one of the Interrupt Status Registers is
updated, the same bit is written to duplicate registers at
addresses 4Ch and 42h. These registers allow a second
management system to access the status data without
worrying about clearing the data. The data in these registers
is for reading only and has no effect on the interrupt output.
Figure 32. Interrupt Register Structure
INT
16 MASK BITS
VALUE
4
5
6
7
VID4/IRQ4
6
7
THERM
VID0–VID4
REGISTERS
CHANNEL
MODE
REGISTER
CONFIGURATION
REGISTER 2
FROM
VALUE
AND LIMIT
REGISTERS
HIGH
LIMIT
1 = OUT
DA
TA
DEMUL
TIPLEXER
INT. TEMP
EXT. TEMP1
FAN1/AIN1
FAN2/AIN2
RESERVED
CI
D1 FAULT
D2 FAULT
2.5V/EXT.
TEMP 2
VCCP1
VCC
+5.0VIN
+12VIN
VCCP2
MASKING
DATA
FROM BUS
INTERRUPT MASK
REGISTERS 1 AND 2
(SAME BIT ORDER AS
STATUS REGISTERS)
MASK GATING y 11
STATUS
BIT
MASK
BIT
INT_ENABLE
INT_CLEAR
CONFIGURATION
REGISTER 1
THERM
CLEAR
THERM
0
1
2
3
4
5
6
7
INTERRUPT
STATUS
REGISTER 2
0
1
2
3
4
5
6
7
INTERRUPT
STATUS
REGISTER 1
HIGH
AND
LOW
LIMIT
COMP
ARA
TORS
LOW
LIMIT
OF
LIMIT
VID2/IRQ2
VID3/IRQ3
VID0/IRQ0
VID1/IRQ1
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